# US 11,994,553 B2 · Signal transmission circuit and method, and integrated circuit (IC)

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- Number: US 11,994,553 B2
- Document ID: US11994553B2
- Status: Granted
- Kind: B2
- Application number: 17/324,995
- Filed: 2021-05-19
- Published: 2021-09-02
- Granted: 2024-05-28
- Earliest claimed: 2018-11-28
- Assignees: Changxin Memory Technologies, Inc.
- Applicants: Changxin Memory Technologies, Inc.
- Inventors: You-Hsien Lin
- Web page: https://patentgrep.com/patent/US11994553B2

## CPC

- G01R 31/2889: {Interfaces, e.g. between probe and tester (G01R31/31905 and G01R1/07364 take precedence)}
- H03K 5/135: by the use of time reference signals, e.g. clock signals
- G01R 31/318513: {Test of Multi-Chip-Moduls}
- H03K 3/037: Bistable circuits
- H03K 17/6871: {the output circuit comprising more than one controlled field-effect transistor}
- H03K 19/0175: Coupling arrangements; Interface arrangements (interface arrangements for digital computers G06F3/00, G06F13/00)
- H03K 19/02: using specified components ({H03K19/0005 - H03K19/0021}, H03K19/003 - H03K19/0175 take precedence)
- H03K 5/1534: Transition or edge detectors
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12)
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A signal transmission circuit and method for testing an integrated circuit (IC) are disclosed. The signal transmission circuit includes: an input circuit, configured to generate a first test signal in response to a first control signal and a clock signal; a transfer chain, including multiple stages of serially-connected transfer circuits, where adjacent transfer circuits in the transfer chain are connected via a through silicon via (TSV), the transfer circuit on one end of the transfer chain is connected to the input circuit, and the multiple stages of transfer circuits transfer the first test signal in stage by stage in response to the clock signal; and multiple signal output ends, where a first test signal input end of each stage of transfer circuit is correspondingly connected to one signal output end. The signal transmission circuit improves the effective utilization rate of a chip in an IC having a TSV test circuit.

## Claims

### Claim 1

A signal transmission circuit configured for testing an integrated circuit (IC), comprising:
an input circuit, configured to generate a first test signal in response to a first control signal and a clock signal;
a transfer chain, comprising multiple stages of serially-connected transfer circuits, wherein adjacent two stages of transfer circuits in the transfer chain are connected via a through silicon via (TSV) therebetween, a transfer circuit on one end of the transfer chain is connected to the input circuit, and the multiple stages of transfer circuits transfer the first test signal stage by stage in response to the clock signal;
multiple signal output ports, wherein a first test signal input port of each stage of transfer circuit is correspondingly connected to one of the multiple signal output ports; and
a mode selection circuit comprising:
a first input port connected to the first test signal;
a second input port connected to a second test signal;
a control port connected to the first control signal;
a first output port connected to the input port of the stage of transfer circuit and configured to transmit the first test signal to the input port of the stage of transfer circuit under a control of the first control signal; and
a second output port connected to an output port of the stage of transfer circuit and configured to transmit the second test signal to the output port of the stage of transfer circuit under the control of the first control signal,
wherein the first test signal and the second test signal are transmitted to an adjacent chip layer via a same TSV, and the second test signal is connected to the multiple signal output ports.

### Claim 2 (depends on 1)

The signal transmission circuit according to claim 1, wherein the input circuit comprises:
a first Flip-Flop, comprising an input pin connected to the first control signal and a clock pin connected to the clock signal; and
an AND gate, comprising a first input pin connected to the first control signal, and a second input pin connected to an inverted output pin of the first Flip-Flop.

### Claim 3 (depends on 1)

The signal transmission circuit according to claim 1, wherein the stage of transfer circuit comprises:
a second Flip-Flop, comprising an input pin connected to the first test signal and a clock pin connected to the clock signal; and
a third Flip-Flop, comprising an input pin connected to an output pin of the second Flip-Flop and a clock pin connected to the clock signal.

### Claim 4 (depends on 3)

The signal transmission circuit according to claim 3, wherein
the adjacent two stages of transfer circuits in the transfer chain are connected via the TSV,
an output pin of the third Flip-Flop of one stage of transfer circuit is connected to a first end of the TSV, and
the input pin of the second Flip-Flop of another stage of transfer circuit is connected to a second end of the TSV.

### Claim 5 (depends on 1)

The signal transmission circuit according to claim 1, wherein
the input circuit is disposed on a base chip layer of the IC, and
the multiple stages of transfer circuits are respectively disposed in each chip layer of the IC.

### Claim 6 (depends on 5)

The signal transmission circuit according to claim 5, further comprising:
a first test TSV chain, comprising multiple serially-connected TSVs and configured to transmit the first control signal from a top chip layer to the base chip layer.

### Claim 7 (depends on 1)

The signal transmission circuit according to claim 1, wherein the mode selection circuit comprises:
a first switch, comprising a first pin connected to an output port of the input circuit, a second pin connected to the input port of the stage of transfer circuit, and a control pin connected to the first control signal; and
a second switch, comprising a first pin connected to the second test signal, a second pin connected to the output port of the stage of transfer circuit, and a control pin connected to the first control signal.

### Claim 8 (depends on 7)

The signal transmission circuit according to claim 7, wherein the first switch includes an N-type metal-oxide-semiconductor field effect transistor (MOSFET), and the second switch includes a P-type MOSFET.

### Claim 9 (depends on 1)

The signal transmission circuit according to claim 1, wherein the mode selection circuit comprises:
a first inverter, comprising an input pin connected to the first control signal;
a second inverter, comprising an input pin connected to an output pin of the first inverter;
a first switch, comprising a first pin connected to the first test signal, a second pin connected to the input port of the stage of transfer circuit, a first control pin connected to the output pin of the first inverter, and a second control pin connected to an output pin of the second inverter; and
a second switch, comprising a first pin connected to the second test signal, a second pin connected to the output port of the stage of transfer circuit, a first control pin connected to the output pin of the second inverter, and a second control pin connected to the output pin of the first inverter,
wherein the first switch and the second switch are complementary metal oxide semiconductor (CMOS) transmission gates.

### Claim 10 (depends on 1)

The signal transmission circuit according to claim 1, wherein
multiple stages of mode selection circuits are respectively disposed in each chip layer of the IC.

### Claim 11 (depends on 10)

The signal transmission circuit according to claim 10, further comprising:
a second test TSV chain, comprising multiple serially-connected TSVs, and configured to provide the first control signal for the multiple stages of mode selection circuits.

### Claim 12

An integrated circuit (IC) testing method, configured for a signal transmission circuit, comprising:
outputting, by an input circuit, a first test signal to an input port of a first stage of transfer circuit in a transfer chain in response to a first control signal and a clock signal, wherein the transfer chain comprises multiple stages of serially-connected transfer circuits, adjacent two stages of transfer circuits in the transfer chain are connected via a through silicon via (TSV) therebetween, and the first stage of transfer circuit is a transfer circuit on one end of the transfer chain connected to the input circuit;
sequentially transmitting, by the multiple stages of transfer circuits, the first test signal along the transfer chain in response to the clock signal;
when the first test signal is transmitted to an output port of a stage of transfer circuit, outputting, by a signal output port connected to an input port of the transfer circuit, the first test signal to a chip layer of the IC; and
transmitting, by a mode selection circuit, the first test signal to the input port of the stage of transfer circuit under a control of the first control signal, or transmitting, by the mode selection circuit, a second test signal to the output port of the stage of transfer circuit under the control of the first control signal, wherein the second test signal is connected to each signal output port, the first test signal and the second test signal are transmitted to an adjacent chip layer via a same TSV, and the mode selection circuit comprises:
a first input port connected to the first test signal;
a second input port connected to the second test signal;
a control port connected to the first control signal;
a first output port connected to the input port of the stage of transfer circuit and configured to transmit the first test signal, and
a second output port connected to an output port of the stage of transfer circuit and configured to transmit the second test signal.

### Claim 13 (depends on 12)

The IC testing method according to claim 12, wherein outputting, by the input circuit, the first test signal to the input port of the first stage of transfer circuit in the transfer chain in response to the first control signal and the clock signal comprises:
outputting the first test signal to the input port of the first stage of transfer circuit in the transfer chain when the first control signal is high.

### Claim 14 (depends on 12)

The IC testing method according to claim 12, wherein sequentially transmitting, by the multiple stages of transfer circuits, the first test signal along the transfer chain in response to the clock signal comprises:
transmitting the first test signal from a previous stage of transfer circuit to a current stage of transfer circuit according to the clock signal when the first control signal is high, wherein the first test signal at an output of the current stage of transfer circuit is delayed by at least one clock cycle from the first test signal at an output of the previous stage of transfer circuit.

### Claim 15 (depends on 12)

The IC testing method according to claim 12, further comprising:
transmitting the second test signal to signal output ports at a plurality of chip layers in the IC when the first control signal is low.

### Claim 16 (depends on 15)

The IC testing method according to claim 15, further comprising:
selectively outputting, by the mode selection circuit, the first test signal sequentially to the plurality of chip layers in the IC or the second test signal simultaneously to the plurality of chip layers in the IC, according to the first control signal.

### Claim 17 (depends on 12)

The IC testing method according to claim 12, further comprising:
transmitting the first control signal from a top chip layer of the IC to a base chip layer of the IC by a first test TSV chain, wherein the first test TSV chain comprises multiple serially-connected TSVs.

### Claim 18 (depends on 12)

The IC testing method according to claim 12, wherein the first test signal has a pulse width of one clock cycle.

### Claim 19

An integrated circuit (IC), comprising a signal transmission circuit, wherein the signal transmission circuit comprises:
an input circuit, configured to generate a first test signal in response to a first control signal and a clock signal;
a transfer chain, comprising multiple stages of serially-connected transfer circuits, wherein adjacent two stages of transfer circuits in the transfer chain are connected via a through silicon via (TSV) therebetween, a transfer circuit on one end of the transfer chain is connected to the input circuit, and the multiple stages of transfer circuits transfer the first test signal stage by stage in response to the clock signal;
multiple signal output ports, wherein a first test signal input port of each stage of transfer circuit is correspondingly connected to one of the multiple signal output ports coupled to one of chip layers of the IC; and
a mode selection circuit comprising:
a first input port connected to the first test signal;
a second input port connected to a second test signal;
a control port connected to the first control signal;
a first output port connected to the input port of the stage of transfer circuit and configured to transmit the first test signal to the input port of the stage of transfer circuit under a control of the first control signal; and
a second output port connected to an output port of the stage of transfer circuit and configured to transmit the second test signal to the output port of the stage of transfer circuit under the control of the first control signal,
wherein the first test signal and the second test signal are transmitted to an adjacent chip layer via a same TSV, and the second test signal is connected to the multiple signal output ports.