Digital oscilloscope having fractional calculus operation and display function

A digital oscilloscope having fractional calculus operation and display function, comprising:

• a digital oscilloscope controller;
• an analog to digital converter (ADC), wherein an input analog signal (a signal being measured) x(t) is sampled and quantified to obtain a sampled data ADC(m), m is the sampling point of the sampled data ADC(m);
• a signal acquisition and storage circuitry, wherein the sampled data ADC(m) is decimated according to a predetermined selected time base, and then under the control of the digital oscilloscope controller, the sampled data after decimation (acquired data) is stored into an acquisition memory ADC RAM of the signal acquisition and storage circuitry in order based on storage address according to a set pre trigger depth and trigger signal, when the acquisition memory ADC RAM is stored full, which means L acquired data is stored, the acquisition and storage is stopped, an oscilloscope data done signal DSO_DONE outputted by the acquisition memory ADC RAM is turned from 0 to 1, at this moment, the acquired data stored in the acquisition memory ADC RAM can be denoted by x(n), 1 is storage address, n=0, 1, 2, . . . , L−1;
• a signal processing and display circuitry;
• and
• a fractional calculus circuitry, which is used for reading out the acquired data x(n) from the acquisition memory ADC RAM to perform a fractional differentiation operation or a fractional integration operation and obtaining a fractional calculus result data y(7), which is sent to the signal processing and display circuitry, in which the acquired data x(n) is turned into a display data and the display data is sent to a LCD for displaying;
• the fractional calculus circuitry comprising:
• a fixed coefficient memory CO RAM, which is used for storing L fixed coefficients c(0),c(1),c(2), . . . , c(L−1) sent from the digital oscilloscope controller, to the jth fixed coefficient c(j), its value is:
• c
• ⁡
• (
• j
• )
• =
• b
• j
• ⁢
• L
• α
• (
• XT
• base
• )
• α
• ,
• j
• =
• 0
• ,
• 1
• ,
• 2
• ,
• …
• ,
• L
• -
• 1
• where L is the number of the pixels at the horizontal direction of the display area of the digital oscilloscope, X is the number of the divisions at the horizontal direction of the display area of the digital oscilloscope, Tbase is the time base of the digital oscilloscope, α is operation order, when α<0, the fractional calculus operation is a fractional integration operation, when α>0, the fractional calculus operation is a fractional differentiation operation, bj is a fixed parameter, its value is:
• b
• j
• =
• (
• 1
• -
• 1
• +
• α
• j
• )
• ⁢
• b
• j
• -
• 1
• ,
• b
• 0
• =
• 1
• N−1 D flip-flop delay units D1, D2, D3, . . . , DN-1, wherein the output of the fixed coefficient memory CO RAM is connected to the input of the 1st D flip-flop delay unit D1, from the 2nd D flip-flop delay unit D2 on, the input of a D flip-flop delay unit is connected to the output of its previous D flip-flop delay unit;
• N fractional operation units THD1, THD2, THD3, . . . , THDN, wherein each fractional operation unit comprises one multiplier and one accumulator (ACC);
• to the pth fractional operation unit THDp, p=1,2, . . . ,N−1, one (port A) of the two inputs of its multiplier MULTIp is connected to the acquired data x(n) outputted by the signal acquisition and storage circuitry, another (port B) of the two inputs of its multiplier MULTIp is connected to the input of the pth flip-flop delay unit Dp, the input of its accumulator ACCp is connected to the output of its multiplier MULTIp, the output of the accumulator ACCp is taken as the output of the pth fractional operation unit THDp;
• to the Nth fractional operation unit THDN, one of the two inputs of its multiplier MULTIN is connected to the acquired data x(n) outputted by the signal acquisition and storage circuitry, another of the two inputs of its multiplier MULTIN is connected to the output of the N−1th D flip-flop delay unit DN-1, the input of its accumulator ACCN is connected to the output of its multiplier MULTIN and
• a fractional operation results memory FO RAM, which is used for storing the operation results of the N fractional operation units THD1, THD2, THD3, . . . , THDN;
• wherein the fractional calculus circuitry is configured to control the fractional operation, when the oscilloscope data done signal DSO_DONE is turned from 0 to 1 is detected, by performing the following steps:
• (1):
• initializing
• initializing fractional operation number i to 1, the flag i_done of the ith fractional calculus operation to 0, fractional operation done signal FO_DONE to 0;
• (2):
• resetting
• resetting the initial values of the N−1 D flip-flop delay units D1, D2, D3, . . . , DN-1 to 0, setting the read address ADDRadecram of the acquisition memory ADC RAM to N*i−1, resetting the read address ADDRcoram of the fixed coefficient memory CO RAM to 0, resetting the initial values of the accumulators of the N fractional operation units THD1, THD2, THD3, . . . , THDN to 0, resetting the write address ADDRforam of the fractional operation results memory FO RAM to 0;
• (3):
• reading data to multiply and accumulate
• driven by a system clock clk, the fractional calculus circuitry initiates an operation of reading the acquisition memory ADC RAM and an operation of reading the fixed coefficient memory CO RAM at each system clock, the total number of reading is k, k=N*i;
• to each reading, the read address ADDRadcram is subtracted by 1, and the read address ADDRcoram is added by 1;
• the data outputted by the read data port of the acquisition memory ADC RAM in chronological order are acquired data x(k−1), . . . , x(1), x(0), namely, the data sent to the port As of the multipliers of the N fractional operation units are acquired data x(k−1) at oth system clock, the data sent to the port As of the multipliers of the N fractional operation units are acquired data x(k−2) at 1 st system clock, the data sent to the port As of the multipliers of the N fractional operation units are acquired data x(k−2) at a system clock, and so on, the data sent to the port As of the multipliers of the N fractional operation units are acquired data x(0) at (k−1)th system clock;
• the data outputted by the read data port of the fixed coefficient memory CO RAM in chronological order are the fixed data c(0), c(1), . . . , c(k−1), the fixed data c(0), c(1), . . . , c(k−1) are serially sent to the N−1 D flip-flop delay units D1, D2, D3, . . . , DN-1 to namely, at oth system clock, the data sent to the port B of the multiplier of the 1st fractional operation unit THD1 is the fixed data c(0), the data sent to the port Bs of the multipliers of the rest of the fractional operation units are 0, at 1° system clock, the data sent to the port Bs of the multipliers of the 1′, the 2TM fractional operation units THD1, THD2 are respectively the fixed data c(1), c(0), the data sent to the port Bs of the multipliers of the rest of the fractional operation units are 0, at 2nd system clock, the data sent to the port Bs of the multipliers of the 1st, the 2nd and the 3rd fractional operation units THD1, THD2, THD2 are respectively the fixed data c(2), c(1), c(0), the data sent to the port Bs of the multipliers of the rest of the fractional operation units are 0, and so on, until at the (k−1)th system clock, the data sent to the port Bs of the multipliers of the N fractional operation units THD1, THD2, THD3, . . . , THDN are respectively c(k−1), . . . , c(2), c(1), c(0);
• after each reading, all the N fractional operation units THD1, THD2, THD3, . . . , THDN perform a multiplying operation and an accumulating operation in turn, when the number of the accumulations reaches k, the ith fractional calculus operation is accomplished, the in fractional operation done signal i_done is turned from 0 to 1;
• (4):
• storing the results of the i″ fractional calculus operation
• when the ith fractional operation done signal i_done is turned from 0 to 1 is detected, the outputs of the N fractional operation units THD1, THD2, THD3, . . . , THDN are taken as the results y(k−1), y(k−2), y(k−3), . . . , y(k-N) of the ith fractional calculus operation and merged into a merged data, the merged data are stored into the fractional operation results memory FO RAM at address ADDRforam under the same system clock clk;
• (5) judging whether a frame of acquired data, namely L acquired data are calculated judging whether the current fractional operation number i is less than L/N, if yes, the write address ADDRforam is added by 1, the current fractional operation number i is added by 1, the i fractional operation done signal i_done is set to 1, then returning to step (2);
• if not, the fractional operation done signal FO_DONE is set to 1, stopping the fractional calculus operation;
• when the fractional operation done signal FO_DONE is turned from 0 to 1 is detected, the digital oscilloscope control controller performs the following steps:
• (1):
• sending the acquired data x(m), n=1, 2, . . . ,L−1 stored in the acquisition memory ADC RAM and the fractional calculus result data y(n), n=1, 2, . . . ,L−1 stored the fractional operation results memory FO RAM to signal processing and display circuitry, in which the acquired data x(n) and the fractional calculus result data y(1) are respectively converted into a display data through a drawing thread, and the two display data are sent to LCD for displaying;
• (2):
• resetting the oscilloscope data done signal DSO_DONE and the fractional operation done signal FO_DONE to 0 to enable the signal acquisition and storage circuitry and the fractional calculus circuitry.