Semiconductor device
AssigneeSamsung Electronics Co., Ltd.
InventorsAhreum Kim, Sunghoon Kim, Daeseok Byeon
Life of this patent
Estimating the term…
Abstract
A semiconductor device includes a substrate, an N-well area formed in the substrate, a first P-channel metal oxide semiconductor (PMOS) transistor having active regions formed in the N-well area, and a first N-channel metal oxide semiconductor (NMOS) transistor having active regions formed in the substrate. The first NMOS transistor includes a first N-type active region overlapping each of the substrate and the N-well area, when viewed from above a plane parallel to a top surface of the substrate.
Claims19
A semiconductor device comprising:
- a substrate;
- an N-well area formed in the substrate;
- a first P-channel metal oxide semiconductor (PMOS) transistor having active regions formed in the N-well area;
- and
- a first N-channel metal oxide semiconductor (NMOS) transistor having active regions formed in the substrate,
- wherein the first NMOS transistor includes a first N-type active region overlapping each of the substrate and the N-well area, when viewed from above a plane parallel to a top surface of the substrate, and
- wherein a first portion of the first N-type active region overlaps the N-well area from above the plane and is a well guard-ring of the N-well area.
A semiconductor device comprising:
- a substrate;
- an N-well area formed in the substrate;
- a first P-type active region formed in the N-well area;
- a second P-type active region formed in the N-well area;
- a first gate formed on the N-well area between the first P-type active region and the second P-type active region;
- a body bias node formed in the N-well area;
- a first N-type active region formed in the substrate;
- a second N-type active region formed in the substrate;
- and
- a second gate formed on the substrate between the first N-type active region and the second N-type active region,
- wherein the body bias node and the first N-type active region are formed of a single continuous active region wherein the body bias node operates as a well guard-ring of the N-well area.
A semiconductor device comprising:
- a substrate;
- an N-well area formed in the substrate;
- a PMOS transistor including active regions formed in the N-well area;
- and
- an NMOS transistor including active regions formed in the substrate and including a first N-type active region,
- wherein the first N-type active region is continuously formed in the N-well area and in a portion of the substrate horizontally adjacent to the N-well area, is used as a source area or a drain area of the NMOS transistor, and is configured to directly provide a body bias of the PMOS transistor to the N-well area, and
- wherein a first portion of the first N-type active region overlaps the N-well area when viewed from above a plane parallel to a top surface of the substrate and is a well guard-ring of the N-well area.
Dependencies are inferred from the claim text.