Computing register with non-volatile-logic data storage
AssigneeTexas Instruments Incorporated
InventorsAdolf Baumann, Mark Jung
Life of this patent
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Abstract
A digital system includes a non-volatile calculating register having a set of latches configured to perform a calculation. A set of non-volatile storage cells is coupled to the set of latches. Access detection logic is coupled to the calculating register and is operable to initiate a calculation of a next value by the calculating register each time the calculating register is accessed by an accessing module. The access detection logic is operable to cause the next value to be stored in the set of non-volatile storage cells at the completion of the calculation as an atomic transaction. After a power loss or other restore event, the contents of the calculating register may be restored from the non-volatile storage cells.
Claims20
A circuit comprising:
- a non-volatile storage array comprising a plurality of non-volatile cells;
- control logic coupled to the non-volatile storage array;
- a computing register coupled to the non-volatile storage array and to the control logic, the computing register comprising a plurality of latches, each of the plurality of latches of the computing register is coupled to a respective one of the plurality of non-volatile cells by a data bus, each latch comprising:
- a first latch portion having an output;
- and
- a second latch portion having a first input port coupled to the output of the first latch portion and a second input port coupled to the respective non-volatile cell, the second latch portion includes an inverter having:
- first and second switches connected in series;
- and
- third and fourth switches connected in series;
- and
- the first and second switches are arranged in parallel with the third and fourth switches.
A circuit comprising:
- a non-volatile storage array comprising a plurality of non-volatile bit cells;
- and
- a plurality of latches, wherein each of the plurality of latches is coupled to a respective non-volatile bit cell of the plurality of non-volatile bit cells by a data bus, each latch comprising:
- a first latch portion having an output;
- and
- a second latch portion having a first input port coupled to the output of the first latch portion and a second input port coupled to the respective non-volatile bit cell, the second latch portion includes:
- first and second transistors coupled in series;
- third and fourth transistors coupled in series, the first and second transistors are arranged in parallel with the third and fourth transistors;
- a fifth transistor coupled to the first and third transistors;
- and
- a sixth transistor coupled to the second and fourth transistors.
Dependencies are inferred from the claim text.