Multi-state programming of memory cells
AssigneeMicron Technology, Inc.
InventorsJeremy M. Hirst, Shanky K. Jain, Hernan A. Castro, Richard K Dodge, William A. Melton
Life of this patent
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Abstract
The present disclosure includes apparatuses, methods, and systems for multi-state programming of memory cells. An embodiment includes a memory having a plurality of memory cells, and circuitry configured to program a memory cell of the plurality of memory cells to one of a plurality of possible data states by applying a voltage pulse to the memory cell, determining the memory cell snaps back in response to the applied voltage pulse, turning off a current to the memory cell upon determining the memory cell snaps back, and applying a number of additional voltage pulses to the memory cell after turning off the current to the memory cell.
Claims20
An apparatus, comprising:
- a memory having a plurality of memory cells;
- and
- circuitry configured to program a memory cell of the plurality of memory cells to one of at least three possible data states by:
- applying a voltage pulse to the memory cell;
- determining the memory cell snaps back in response to the applied voltage pulse;
- turning off a current to the memory cell upon determining the memory cell snaps back;
- and
- applying a number of additional voltage pulses to the memory cell after turning off the current to the memory cell, wherein each of the number of additional voltage pulses have a same magnitude.
An apparatus, comprising:
- a memory having a plurality of memory cells;
- and
- circuitry configured to program a memory cell of the plurality of memory cells to one of at least three possible data states by:
- applying a voltage pulse to the memory cell;
- determining the memory cell snaps back in response to the applied voltage pulse;
- turning off a current to the memory cell upon determining the memory cell snaps back;
- and
- applying a single additional voltage pulse to the memory cell after turning off the current to the memory cell, wherein a duration of the single additional voltage pulse is shorter than a duration of the voltage pulse, and wherein the single additional voltage pulse has a same magnitude for the duration of the single additional voltage pulse.
A method of operating memory, comprising:
- programming a memory cell to one of at least three possible data states by:
- applying a voltage pulse to the memory cell;
- determining the memory cell snaps back in response to the applied voltage pulse;
- turning off a current to the memory cell upon determining the memory cell snaps back;
- and
- applying one additional voltage pulse to the memory cell after turning off the current to the memory cell, wherein the one additional voltage pulse has a same magnitude for a duration of the one additional voltage pulse;
- or
- applying two additional voltage pulses to the memory cell after turning off the current to the memory cell, wherein each of the two additional voltage pulses have a same magnitude.
Dependencies are inferred from the claim text.