Device for packet processing acceleration
AssigneeRealtek Semiconductor Corp.
InventorKuo-Cheng Lu
Life of this patent
Estimating the term…
Abstract
A device for packet processing acceleration includes a CPU, a tightly coupled memory (TCM), a buffer descriptor (BD) prefetch circuit, and a BD write back circuit. The BD prefetch circuit reads reception-end (RX) BDs from an RX BD ring of a memory to write them into an RX ring of the TCM, and reads RX header data from a buffer of the memory to write them into the RX ring. The CPU accesses the RX ring to process the RX BDs and RX header data, and generates transmission-end (TX) BDs and TX header data; afterwards, the CPU writes the TX BDs and TX header data into a TX ring of the TCM. The BD write back circuit reads the TX BDs and TX header data from the TX ring, writes the TX BDs into a TX BD ring of the memory, and writes the TX header data into the buffer.
Claims15
A device for packet processing acceleration comprising a central processing unit (CPU), a tightly coupled memory (TCM), a buffer descriptor (BD) prefetch circuit, and a BD write back circuit, wherein:
- the TCM is coupled to the CPU;
- the BD prefetch (BDP) circuit is coupled to the TCM, and configured to read multiple pieces of reception-end (RX) BD data stored in an RX BD ring according to a BD extraction map and then write the multiple pieces of RX BD data into an RX packet information ring;
- and the BDP circuit is further configured to read multiple pieces of RX header data stored in a packet buffer according to a buffer extraction map, and then write the multiple pieces of RX header data into the RX packet information ring, wherein both the RX BD ring and the packet buffer are included in a system memory and the RX packet information ring is included in the TCM;
- the CPU is configured to access the RX packet information ring to read and process the multiple pieces of RX BD data and the multiple pieces of RX header data and thereby generate multiple pieces of transmission-end (TX) BD data and multiple pieces of TX header data;
- and the CPU is further configured to write the multiple pieces of TX BD data and the multiple pieces of TX header data into a TX packet information ring, wherein the TX packet information ring is included in the TCM;
- and
- the BD write back (BDW) circuit is coupled to the TCM, and configured to read the multiple pieces of TX BD data stored in the TX packet information ring and then write the multiple pieces of TX BD data into a TX BD ring;
- and the BDW circuit is further configured to read the multiple pieces of TX header data stored in the TX packet information ring and then write the multiple pieces of TX header data into the packet buffer, wherein the TX BD ring is included in the system memory.
A device for packet processing acceleration comprising a central processing unit (CPU) and a tightly coupled memory (TCM), wherein:
- the TCM is coupled to the CPU;
- the CPU is configured to perform a buffer descriptor prefetch (BDP) operation including:
- the CPU reading multiple pieces of reception-end (RX) buffer descriptor (BD) data stored in an RX BD ring according to a BD extraction map and then writing the multiple pieces of RX BD data into an RX packet information ring;
- and the CPU reading multiple pieces of RX header data stored in a packet buffer according to a buffer extraction map, and then writing the multiple pieces of RX header data into the RX packet information ring, wherein both the RX BD ring and the packet buffer are included in a system memory and the RX packet information ring is included in the TCM;
- the CPU is configured to perform a BD processing operation including:
- the CPU accessing the RX packet information ring to read and process the multiple pieces of RX BD data and the multiple pieces of RX header data and thereby generating multiple pieces of transmission-end (TX) BD data and multiple pieces of TX header data;
- and the CPU writing the multiple pieces of TX BD data and the multiple pieces of TX header data into a TX packet information ring, wherein the TX packet information ring is included in the TCM;
- and
- the CPU is configured to perform a BD write back (BDW) operation including:
- the CPU reading the multiple pieces of TX BD data stored in the TX packet information ring and then writing the multiple pieces of TX BD data into a TX BD ring;
- and the CPU reading the multiple pieces of TX header data stored in the TX packet information ring and then writing the multiple pieces of TX header data into the packet buffer, wherein the TX BD ring is included in the system memory.
Dependencies are inferred from the claim text.