Semiconductor device patterning methods
AssigneeApplied Materials, Inc.
InventorsYong Wang, Doreen Wei Ying Yong, Bhaskar Jyoti Bhuyan, John Sudijono
Life of this patent
Estimating the term…
Abstract
Methods of patterning semiconductor devices comprising selective deposition methods are described. A blocking layer is deposited on a metal surface of a semiconductor device before deposition of a dielectric material on a dielectric surface. Methods include exposing a substrate surface including a metal surface and a dielectric surface to a heterocyclic reactant comprising a headgroup and a tailgroup in a processing chamber and selectively depositing the heterocyclic reactant on the metal surface to form a passivation layer, wherein the heterocyclic headgroup selectively reacts and binds to the metal surface.
Claims12
A semiconductor device patterning method comprising:
- in a substrate processing chamber, exposing a semiconductor device substrate surface including a metal surface and a dielectric surface to a vapor phase heterocyclic reactant comprising a heterocyclic headgroup selected from the group consisting of a phosphinine group, a phosphinoline group, and a phosphole group, and a tailgroup comprising a carbon chain having a length in the range of from 1 to 50 carbon atoms;
- in the substrate processing chamber, selectively depositing the vapor phase heterocyclic reactant on the metal surface to cover the metal surface with a blocking layer, wherein the heterocyclic headgroup selectively binds to the metal surface;
- in the substrate processing chamber, depositing a dielectric material on the dielectric surface not covered by the blocking layer at a dielectric deposition temperature up to 350° C. at which the heterocyclic reactant remains bound to the metal surface and maintains stability;
- and
- decomposing the blocking layer covering the metal surface in the substrate processing chamber at temperature higher than the dielectric deposition temperature to form a pattern on the semiconductor device substrate surface.
A semiconductor device patterning method comprising:
- in a substrate processing chamber, exposing a semiconductor device substrate surface including a metal surface and a dielectric surface to a heterocyclic reactant comprising a headgroup and a tailgroup;
- selectively depositing the heterocyclic reactant on the metal surface to form a blocking layer, wherein the heterocyclic headgroup is selected from the group consisting of a phosphinine group, a phosphinoline group, and a phosphole group, the heterocyclic group selectively binds to the metal surface, and wherein the tailgroup comprises a carbon chain and the carbon chain has a length is in the range of from 1 to 50 carbon atoms;
- in the substrate processing chamber, depositing a dielectric material on the dielectric surface not covered by the blocking layer at a dielectric deposition temperature;
- and
- decomposing the blocking layer covering the metal surface in the substrate processing chamber at temperature higher than the dielectric deposition temperature to form a pattern on the semiconductor device substrate surface.
Dependencies are inferred from the claim text.