Tuning voltage tracker for receive/transmit phase-locked loop (PLL) fast switching

A phase-locked loop (PLL) circuit comprising:

• a charge pump;
• a voltage-controlled oscillator (VCO) having a control input coupled to an output of the charge pump via a node;
• and
• a tracking circuit comprising a sample-and-hold circuit coupled to the node and configured to sample a voltage of the node during a mission mode, save a representation of the sampled voltage before entering a standby mode, and restore the sampled voltage to the node for reentering the mission mode using the saved representation of the sampled voltage, wherein the tracking circuit further comprises a successive-approximation register (SAR) analog-to-digital converter (ADC) having an input coupled to an output of the sample-and-hold circuit.

A radio frequency transceiver circuit comprising:

• a receive path;
• a receive phase-locked loop (RxPLL) coupled to the receive path;
• a transmit path;
• and
• a transmit phase-locked loop (TxPLL) coupled to the transmit path, wherein at least one of the RxPLL or the TxPLL comprises:
• a charge pump;
• a voltage-controlled oscillator (VCO) having a control input coupled to an output of the charge pump via a node;
• and
• a tracking circuit coupled to the node and configured to sample a voltage of the node during a mission mode, save a representation of the sampled voltage before entering a standby mode, and restore the sampled voltage to the node for reentering the mission mode using the saved representation of the sampled voltage.

A method of wireless communication, comprising:

• operating a first phase-locked loop (PLL) during a first mission mode for a first circuit path associated with the first PLL;
• sampling a control voltage of the first PLL during the first mission mode;
• saving a representation of the sampled control voltage of the first PLL before entering a first standby mode for the first circuit path;
• stopping operation of at least a portion of the first PLL during the first standby mode;
• and
• restoring the sampled control voltage to the first PLL for reentering the first mission mode using the saved representation of the sampled control voltage of the first PLL, wherein the first circuit path comprises a receive path or a transmit path, wherein the first PLL comprises a receive phase-locked loop (RxPLL) or a transmit phase-locked loop (TxPLL), and wherein the first mission mode is for reception of a downlink (DL) signal or transmission of an uplink (UL) signal.