Clock alignment and uninterrupted phase change systems and methods

A method comprising:

• receiving, at processing circuitry of a clock alignment loop, a first alignment signal indicative of a first timing difference between a reference clock signal and a data signal at a circuit of interest;
• changing, via the processing circuitry, a programmable time delay of the data signal;
• receiving, at the processing circuitry, a second alignment signal indicative of a second timing difference between the reference clock signal and the data signal at the circuit of interest, the second timing difference based at least in part on the programmable time delay;
• comparing, via the processing circuitry, the first alignment signal and the second alignment signal;
• and
• aligning the reference clock signal and the data signal at the circuit of interest via an aligned value of the programmable time delay based at least in part on comparing of the first alignment signal and the second alignment signal.

An electronic device comprising:

• first logic circuitry comprising a logic input configured to receive a data signal and a logic output configured to output a processed data signal to second logic circuitry, the first logic circuitry causing a first delay between the logic input and the logic output;
• the second logic circuitry comprising phase detection circuitry configured to receive the processed data signal, receive a reference clock signal, and output an alignment signal associated with a relative timing between the reference clock signal and the processed data signal;
• phase select circuitry comprising a string of buffers configured to effect a second delay on the data signal based at least in part on a number of buffers implemented in the string of buffers;
• and
• a loop controller configured to select the number of buffers to implement in the string of buffers based at least in part on the alignment signal.