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US 11,984,888 B2Granted
Circuits and methods to harvest energy from transient on-chip data
AssigneeMetis Microsystems, LLC
InventorAzeez Bhavnagarwala
Life of this patent
Estimating the term…
Abstract
Circuits and methods that harvest electrostatic energy from transient on-chip data are described in the Application. In one aspect, a method and inverter circuit harvests electrostatic charge held at its output node at an electric potential comparable to the power supply voltage rail to a common grid/node as the output makes a 1→0 logic transition. This charge harvested at a common grid/node can be used by circuits (described in applications 63/090,169, 63/139,744) to drive 0→1 logic transition at their output nodes at lower energy drain from the on-chip power grid than a conventional CMOS inverter would with similar performance, slew rates at inverter input and output and with similar output driving transistor geometries.
Claims20
An apparatus, comprising:
- an inverter having an input terminal and an output terminal;
- a first N-channel field effect transistor (NFET) and a first P channel field effect transistor (PFET) with their drain terminals shorted together at the output terminal of the inverter, a source terminal of the first NFET and a source terminal of the first PFET are connected to a ground and a power supply, respectively;
- a second PFET having a source terminal and a drain terminal configured to couple the output terminal of the inverter to a harvest terminal whose capacitance holds harvested charge at a voltage lower than a voltage of the power supply;
- the input terminal and the output terminal of the inverter, during operation, having electric potentials making full-swing transitions between the voltage of the power supply and a voltage of the ground, the input terminal of the inverter connected directly to a gate input terminal of the first PFET;
- a second NFET having a gate input terminal configured to be driven by the input terminal of the inverter and having a source terminal and a drain terminal connected to the ground and the output terminal of the inverter, respectively;
- and
- a 2-input NAND gate with its inputs configured to be driven by the input terminal and the output terminal of the inverter, the 2-input NAND gate having an output terminal configured to drive a gate input terminal of the second PFET and an input terminal of a delay element having an inverted output configured to drive the first NFET of the inverter.
4 more elements
An apparatus comprising:
- an inverter including a power supply, ground, a p-channel field effect transistor (PFET), an n-channel field effect transistor (NFET), a harvest terminal, an input terminal and an output terminal,
- the inverter configured to be responsive to a low-to-high transition at the input terminal and configured to (1) electrically couple, via the PFET, the output terminal to the harvest terminal in response to an electric potential at the output terminal approximately exceeding an electric potential at the harvest terminal, and (2) electrically couple, via the NFET, the output terminal to ground while decoupling, via the PFET, the output terminal from the harvest terminal in response to the electric potential at the output terminal being approximately less than or equal to the electric potential at the harvest terminal.
An apparatus, comprising:
- an inverter having an input terminal and an output terminal;
- a first P-channel field-effect transistor (PFET);
- a second PFET connected in series with the first PFET, the first PFET having a source terminal configured to be connected to a power supply and having a gate terminal connected to the input terminal of the inverter, the second PFET having a source terminal configured to be connected to the output terminal of the inverter and a drain terminal configured to be connected to a harvest terminal;
- an N-channel field-effect transistor (NFET) having a drain terminal connected to a drain terminal of the first PFET and to the output terminal of the inverter, the NFET having a source terminal configured to be connected to a ground;
- and
- a NAND gate including a first NAND input terminal and a second NAND input terminal, the first NAND input terminal and the second NAND input terminal of the NAND gate being connected with and configured to be driven by the input terminal of the inverter and the output terminal of the inverter, the NAND gate having an output terminal connected with a gate input terminal of the second PFET and an input terminal of a delay element that has an inverted output terminal configured to be connected with the NFET of the inverter, the NAND gate configured to generate an active low pulse at the output terminal of the NAND gate.
3 more elements
Dependencies are inferred from the claim text.