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US 11,984,887 B2Granted
Circuits and methods to use energy harvested from transient on-chip data
AssigneeMetis Microsystems, LLC
InventorAzeez Bhavnagarwala
Life of this patent
Estimating the term…
Abstract
Circuits and methods that use harvested electrostatic energy from transient: on-chip data are described in the Application. In one aspect, a method inverter circuit use harvested electrostatic charge held at any electric potential higher than the common ground reference potential of CMOS circuits in a chip, to partially drive a 0→1 logic transition at the output of the inverter at lower energy drain from the on-chip power grid than a conventional CMOS inverter with similar performance, slew rates at inverter input and output and with similar output driving transistor geometries.
Claims20
An inverter, comprising:
- a first N-channel field effect transistors (NFET) and a first P-channel field effect transistors (PFET) with their drain terminals shorted together at an output terminal of the inverter, a source terminal of the first NFET being connected to a ground, a source terminal of the first PFET being connected to a power supply;
- a second NFET having a source terminal and a drain terminal coupled to the output terminal with a grid/node having a capacitance configured to hold harvested charge at a voltage larger than a reference ground potential at the ground;
- an input terminal and the output terminal of the inverter configured such that electric potentials make full-swing transitions between a voltage of the power supply and a voltage of the ground, the input terminal of the inverter connected directly to a gate input terminal of the first NFET;
- a second PFET having (1) a gate input terminal configured to be driven by the input terminal of the inverter, (2) a source terminal that is connected to the power supply, and (3) a drain terminal that is connected to the output terminal of the inverter;
- and
- a 2-input NOR gate having inputs configured to be driven by the input terminal and the output terminal of the inverter, an output of the 2-input NOR gate configured to drive the gate input terminal of the second NFET and the input terminal of a delay element that is configured to have an inverted output that drives the first PFET.
3 more elements
An apparatus, comprising:
- an inverter that includes a power supply, an input terminal an output terminal, a p-channel field effect transistor (PFET), an n-channel field effect transistor (NFET), and a harvest terminal,
- the inverter configured to be responsive to a high-to-low transition at the input terminal and configured to (1) electrically couple, via the NFET, the output terminal to the harvest terminal until an electric potential at the output terminal approaches an electric potential of the harvest terminal, and (2) electrically couple, via the PFET, the power supply to the output terminal while decoupling, via the NFET, the output terminal from the harvest terminal in response to the electric potential at the output terminal increasing to a voltage approximately less than or equal to the electric potential at the harvest terminal.
An apparatus, comprising:
- an inverter having an input terminal and an output terminal;
- a first N-channel field-effect transistor (NFET);
- a second NFET connected in series with the first NFET, the first NFET having a source terminal configured to be connected to ground and having a gate terminal connected to the input terminal of the inverter, the second NFET having a source terminal configured to be connected to the output terminal of the inverter and a drain terminal configured to be connected to a harvest terminal;
- a P-channel field-effect transistor (PFET) having a drain terminal connected to a drain terminal of the first NFET and at the output terminal of the inverter, the PFET having a source terminal configured to be connected to a power supply terminal;
- and
- a NOR gate with a first NOR input terminal and a second NOR input terminal, the first NOR input terminal and the second NOR input terminal of the NOR gate being connected with and configured to be driven by the input terminal of the inverter and the output terminal of the inverter, the NOR gate having an output terminal connected with a gate input terminal of the second NFET and an input terminal of an inverting delay element whose output terminal configured to be connected with the PFET of the inverter, the NOR gate configured to generate an active high pulse at the output terminal of the NOR gate.
3 more elements
Dependencies are inferred from the claim text.