Chopper amplifying circuit employing negative impedance compensation technique

A chopper amplifying circuit employing a negative impedance compensation technique, comprising:

• a differential input end, a first-level chopper switch, a negative impedance converting circuit, a first-level amplifying circuit, a second-level chopper switch, a second-level amplifying circuit, a differential output end, a negative feedback unit, and input capacitors, wherein two ports of the differential input end are respectively connected to two input terminals of the first-level chopper switch for inputting a differential voltage signal;
• two output terminals of the first-level chopper switch are respectively connected to two signal input ends of the first-level amplifying circuit through the input capacitors;
• two signal output ends of the first-level amplifying circuit are respectively connected to two input terminals of the second-level chopper switch, two output terminals of the second-level chopper switch are respectively connected to two signal input ends of the second-level amplifying circuit, and two signal output ends of the second-level amplifying circuit are respectively connected to two ports of the differential output end, and are also connected to a feedback input end of the first-level amplifying circuit through the negative feedback unit;
• and the negative impedance converting circuit is parallel-connected to the two signal input ends of the first-level amplifying circuit for reducing an equivalent input capacitance of the first-level amplifying circuit.