Active DC bus voltage balancing circuit

A system, comprising:

• a DC bus circuit having a first bus terminal, a second bus terminal, a first bus capacitor, and a second bus capacitor, the first and second bus capacitors coupled in series with one another between the first and second bus terminals, and the first and second bus capacitors are coupled to one another at an intermediate node;
• a first depletion mode field effect transistor (FET) coupled between the first bus capacitor and a first switching control circuit;
• a second depletion mode FET coupled between the second bus capacitor and a second switching control circuit;
• and
• a control circuit configured to control the first and second depletion mode FETs to balance a first capacitor voltage of the first bus capacitor and a second capacitor voltage of the second bus capacitor;
• wherein:
• the first switching control circuit is configured to turn the first depletion mode FET off responsive to the first capacitor voltage being less than or equal to the second capacitor voltage;
• the second switching control circuit is configured to turn the second depletion mode FET off responsive to the first capacitor voltage being greater than or equal to the second capacitor voltage;
• a drain of the first depletion mode FET is coupled to the first bus terminal;
• the first switching control circuit includes a first discharge circuit branch coupled between a source of the first depletion mode FET and the intermediate node;
• a drain of the second depletion mode FET is coupled to the intermediate node;
• and
• the second switching control circuit includes a second discharge circuit branch coupled between a source of the second depletion mode FET and the second bus terminal.

A system, comprising:

• a DC bus circuit having a first bus terminal, a second bus terminal, a first bus capacitor, and a second bus capacitor, the first and second bus capacitors coupled in series with one another between the first and second bus terminals, and the first and second bus capacitors are coupled to one another at an intermediate node;
• a first depletion mode field effect transistor (FET) coupled between the first bus capacitor and a first switching control circuit;
• a second depletion mode FET coupled between the second bus capacitor and a second switching control circuit;
• and
• a control circuit configured to control the first and second depletion mode FETs to balance a first capacitor voltage of the first bus capacitor and a second capacitor voltage of the second bus capacitor;
• wherein the control circuit includes:
• a voltage sense circuit configured to sense the first capacitor voltage of the first bus capacitor and the second capacitor voltage of the second bus capacitor, and provide a sensor voltage signal based on the first and second capacitor voltages;
• and a regulator configured to control the first and second depletion mode FETs based on the sensor voltage signal;
• and
• wherein the regulator is configured to provide a control output voltage signal based on the sensor voltage signal, the control output voltage signal having a zero amplitude responsive to the first and second capacitor voltages being equal, a positive amplitude responsive to the first capacitor voltage being greater than the second capacitor voltage, and a negative amplitude responsive to the first capacitor voltage being less than the second capacitor voltage.

A system, comprising:

• a DC bus circuit having a first bus terminal, a second bus terminal, a first bus capacitor, and a second bus capacitor, the first and second bus capacitors coupled in series with one another between the first and second bus terminals, and the first and second bus capacitors and are coupled to one another at an intermediate node;
• a first depletion mode field effect transistor (FET) coupled between the first bus capacitor and a first switching control circuit;
• a second depletion mode FET coupled between the second bus capacitor and a second switching control circuit;
• and
• a control circuit configured to control the first and second depletion mode FETs to balance a first capacitor voltage of the first bus capacitor and a second capacitor voltage of the second bus capacitor;
• wherein the first and second depletion mode FETs are configured to discharge the respective first and second bus capacitors responsive to a power supply having an output voltage being less than a threshold;
• wherein the system includes a motor drive, comprising:
• a rectifier having an output;
• the DC bus circuit;
• an inverter;
• the first depletion mode field effect transistor (FET);
• and
• the second depletion mode FET;
• wherein the control circuit includes a voltage sense circuit configured to sense the first capacitor voltage and the second capacitor voltage, and provide a sensor voltage signal based on the first and second capacitor voltages, and a regulator configured to control the first and second depletion mode FETs based on the sensor voltage signal;
• and
• wherein the regulator is configured to provide a control output voltage signal based on the sensor voltage signal, the control output voltage signal having a zero amplitude responsive to the first and second capacitor voltages being equal, a positive amplitude responsive to the first capacitor voltage being greater than the second capacitor voltage, and a negative amplitude responsive to the first capacitor voltage being less than the second capacitor voltage.