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US 11,984,504 B2Granted
Power transistor IC with thermopile
AssigneeTexas Instruments Incorporated
InventorsHenry Litzmann Edwards, Andres Arturo Blanco, Orlando Lazaro
Life of this patent
Estimating the term…
Abstract
IC apparatus, and manufacturing methods therefor, that include a power transistor and a thermoelectric device. The power transistor is constructed in a plurality of layers formed over a semiconductor substrate. The thermoelectric device is formed in one or more of the plurality of layers and is sensitive to temperature differences within the IC apparatus resulting from operation of the power transistor.
Claims15
An integrated circuit (IC) apparatus, comprising:
- a power transistor constructed in a plurality of layers formed in or over a semiconductor substrate;
- an n-type isolation tank at least partially formed by one or more of the plurality of layers, the power transistor contained within the n-type isolation tank;
- and
- a thermoelectric device formed in one or more of the plurality of layers, the thermoelectric device including an n-type thermopile formed by an n-type doped portion of a periphery of the power transistor within the n-type isolation tank.
1 more element
An integrated circuit, comprising:
- a power transistor constructed in a plurality of layers formed in or over a p-type semiconductor substrate;
- and
- a thermoelectric device formed in one or more of the plurality of layers, the thermoelectric device including a p-type thermopile having p-type ohmic connections extending through ones of the plurality of layers between a top surface of an uppermost active semiconductor layer of the plurality of layers and a bulk portion of the semiconductor substrate,
- wherein each p-type ohmic connection is collectively formed by corresponding portions of:
- a p-doped active semiconductor region formed in one of the plurality of layers that also contains p-type source/drain regions of the power transistor, wherein the p-doped active semiconductor region has the same dopant concentration as the p-type source/drain regions;
- and
- a p-type shallow well formed in one of the plurality of layers.
4 more elements
An integrated circuit (IC), comprising:
- a power transistor constructed in a plurality of layers formed in or over a p-type semiconductor substrate;
- and
- a thermoelectric device formed in one or more of the plurality of layers, the thermoelectric device including a p-type thermopile having p-type ohmic connections extending through ones of the plurality of layers between a top surface of an uppermost active semiconductor layer of the plurality of layers and a bulk portion of the semiconductor substrate,
- wherein:
- the power transistor is surrounded by a trench extending through the plurality of layers into the bulk portion of the semiconductor substrate;
- and
- the p-type ohmic connections are formed by corresponding conductive portions of the trench.
4 more elements
An integrated circuit (IC), comprising:
- a power transistor constructed in a plurality of layers formed in or over a semiconductor substrate;
- and
- a thermoelectric device formed in one or more of the plurality of layers,
- wherein:
- the power transistor is one of an array of power transistors separated into a plurality of transistor banks by isolation structures;
- the thermoelectric device is one of plurality of a p-type thermopiles each comprising p-type ohmic connections extending through ones of the plurality of layers between:
- a top surface of an uppermost active semiconductor layer of the plurality of layers;
- and
- a different corresponding portion of a bulk portion of the semiconductor substrate;
- and
- the p-type ohmic connections are laterally disposed in a pattern based on equithermal lines of the array.
8 more elements
Dependencies are inferred from the claim text.