Quadrature circuit interconnect architecture with clock forwarding

A method of integrated circuit communication, the method comprising:

• transmitting a clock signal via a clock lane and at a first rate from a first chip to a second chip;
• dividing the transmitted clock signal via a clock divider at the second chip to form a first divided clock signal and a second divided clock signal having reduced rates compared to the first rate;
• maintaining, via the clock divider, current mode logic properties for the first and second divided clock signals;
• and
• inputting the first divided clock signal and the second divided clock signal into multiple receivers of the first chip, wherein each of the multiple receivers comprises its own de-skew circuit and the inputting into the multiple receivers occurs into the de-skew circuits.

An integrated circuit communication architecture comprising:

• a clock lane configured to send a clock signal at a first rate from a first chip to a second chip;
• a clock divider on the second chip, the clock divider configured to receive the clock signal sent via the clock lane and to create and send a first divided clock signal and a second divided clock signal from the received clock signal, the first divided clock signal and the second divided clock signal being sent at reduced rates compared to the first rate;
• and
• first and second receivers on the second chip, the first receiver including a first de-skew circuit, the second receiver including a second de-skew circuit, wherein the first and second de-skew circuits are configured to receive and process the first divided clock signal and the second divided clock signal from the clock divider to allow for sampling of data transmitted from the first chip to the second chip;
• wherein the clock divider is configured to serve both the first receiver and the second receiver with each of the first divided clock signal and the second divided clock signal.