Method and wire-line transceiver for performing serial loop back test
AssigneeSamsung Electronics Co., Ltd.
InventorsVishal Khatri, Tamal Das, Umamaheswara Reddy Katta
Life of this patent
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Abstract
A wire-line transceiver is configured to perform a serial loop back test. The wire-line transceiver includes an on-chip transmitter, an on-chip receiver and a fractional feed forward equalizer circuit (fractional FFE circuit) in a serial loop back line path between the on-chip transmitter and the on-chip receiver. The fractional FFE circuit is configured to induce a delay one of less than one symbol time of data, for enhancing an eye opening from the serial loop back line during the serial loop back test, compared to a situation where the fractional FFE circuit is not present or is not used.
Claims10
A wire-line transceiver for performing a serial loop back test, the wire-line transceiver comprising:
- an on-chip transmitter;
- an on-chip receiver;
- and
- a fractional feed forward equalizer circuit (fractional FFE circuit) in a serial loop back line path between the on-chip transmitter and the on-chip receiver, wherein the fractional FFE circuit is configured to:
- induce a delay of less than one symbol time of data, for enhancing an eye opening from the serial loop back line during the serial loop back test, compared to a situation where the fractional FFE circuit is not present or is not used.
A method for performing a serial loop back test in a wire-line transceiver, the method comprising:
- sending, by an on-chip transmitter of the wire-line transceiver, data to an on-chip receiver for performing the serial loop back test;
- inducing, by a fractional feed forward equalizer circuit (fractional FFE circuit) of the wire-line transceiver, a delay of less than one symbol time of data, thereby enhancing an eye opening from a serial loop back line during the serial loop back test compared to a situation where the fractional FFE circuit is not present or is not used;
- and
- performing, by the wire-line transceiver, the serial loop back test with the enhanced eye opening from the serial loop back line,
- wherein the fractional FFE circuit is located in a serial loop back line path between the on-chip transmitter and the on-chip receiver.
Dependencies are inferred from the claim text.