US 11,979,173 B2Granted

Single-ended direct interface dual DAC feedback photo-diode sensor

AssigneeSigmasense, LLC.

InventorPhuong Huynh

Life of this patent

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Abstract

An analog to digital converter (ADC) that is configured to service a photo-diode includes a capacitor and a self-referenced latched comparator. The capacitor produces a photo-diode voltage based on charging by a photo-diode current associated with the photo-diode and a digital to analog converter (DAC) source current and/or a DAC sink current. The self-referenced latched comparator generates a first digital signal that is based on a difference between the photo-diode voltage and a threshold voltage associated with the self-referenced latched comparator. Also, one or more processing modules executes operational instructions to process the first digital signal to generate a second digital signal and/or a third digital signal. An N-bit DAC generates the DAC source current based on the second digital signal, and an M-bit DAC generates the DAC sink current based on the third digital signal. The DAC source current and/or the DAC sink current tracks the photo-diode current.

Claims20

Dependent claims

An analog to digital converter (ADC) comprising:

a capacitor that is operably coupled to a photo-diode and configured to produce a photo-diode voltage based on charging by at least one of a photo-diode current associated with the photo-diode and at least one of a digital to analog converter (DAC) source current or a DAC sink current, wherein the ADC is coupled to the photo-diode via a single line;
a self-referenced latched comparator operably coupled to the photo-diode and the capacitor and configured to generate a first digital signal that is based on the photo-diode voltage, wherein the DAC sink current configured to maintain a voltage at an input of the self-referenced latched comparator at a threshold voltage associated with the self-referenced latched comparator based on no photo-diode current being provided from the photo-diode;
memory that stores operational instructions;
and
one or more processing modules that is operably coupled to the self-referenced latched comparator and the memory and configured to execute the operational instructions to process the first digital signal to generate at least one of a second digital signal or a third digital signal that control the at least one of the DAC source current or a DAC sink current.

2 more elements

An analog to digital converter (ADC) comprising:

a capacitor that is operably coupled to a photo-diode and configured to produce a photo-diode voltage based on charging by at least one of a photo-diode current associated with the photo-diode and at least one of a digital to analog converter (DAC) source current or a DAC sink current, wherein the ADC is coupled to the photo-diode via a single line;
a self-referenced latched comparator operably coupled to the photo-diode and the capacitor and configured to generate a first digital signal that is based on a difference between the photo-diode voltage and a threshold voltage associated with the self-referenced latched comparator;
memory that stores operational instructions;
and
one or more processing modules that is operably coupled to the self-referenced latched comparator and the memory and configured to execute the operational instructions to process the first digital signal to generate at least one of a second digital signal or a third digital signal that control the at least one of the DAC source current or a DAC sink current.

2 more elements

Dependencies are inferred from the claim text.

Facts

Application: 18/103,614Filed 31 Jan 2023 · continuation
Priority: 8 Nov 2019
Published: US 2023/0170918 A11 Jun 2023
Granted: 7 May 2024
Term ends: Not estimatedThe source records don’t support an estimate.

Classification8 codes

H03M 3/462
Analogue/digital converters using delta-sigma modulation as an intermediate step: details relating to the decimation process
H03M 1/0626
Characterised by the use of methods or means not specific to a particular type of detrimental influence: by filtering
H03M 3/32
Delta-sigma modulation: with special provisions or arrangements for power saving, e.g. by allowing a sleep mode, using lower supply voltage for…
H03M 3/476
Analogue/digital converters using delta-sigma modulation as an intermediate step: non-linear conversion systems

Family

Application16/678,793Parent of this continuation-in-part · filed 8 Nov 2019
Application17/078,187Parent of this continuation-in-part · filed 23 Oct 2020
US 10,862,492 B1Parent of this continuation-in-part · filed 8 Dec 2020
Application17/132,241Parent of this continuation · filed 23 Dec 2020
US 11,133,811 B2Parent of this continuation-in-part · filed 28 Sep 2021
Application17/530,639Parent of this continuation · filed 19 Nov 2021
US 11,190,205 B2Parent of this continuation · filed 30 Nov 2021
US 2023/0170918 A1Pre-grant publication · published 1 Jun 2023
US 11,595,054 B2Parent of this continuation
Application17/132,241Parent of this continuation-in-part
US 2021/0143827 A1Published application
US 2021/0152182 A1Published application
US 2022/0085826 A1Published application
US 11,979,173 B2This patent

From the US filing history. Foreign family members aren’t listed.