Leakage compensation dynamic register, data operation unit, chip, hash board, and computing apparatus

A leakage compensation dynamic register, comprising:

• an input terminal for inputting data;
• an output terminal for outputting the data;
• a clock signal terminal for supplying a clock signal;
• an analog switch unit for transmitting the data under control of the clock signal;
• a data latch unit for latching the data under control of the clock signal;
• and
• an output drive unit for inverting and outputting the data received from the data latch unit;
• the analog switch unit, the data latch unit and the output drive unit being sequentially connected in series between the input terminal and the output terminal, and the analog switch unit and the data latch unit having a node therebetween;
• and
• the leakage compensation dynamic register further comprises a leakage compensation unit electrically connected between the node and the output terminal, the leakage compensation unit has a first terminal electrically connected to the output terminal, a second terminal electrically connected to the node, and a control terminal;
• wherein the leakage compensation unit comprises a PMOS transistor having a source terminal electrically connected to the output terminal, a drain terminal electrically connected to the node, and a gate terminal electrically connected to a power supply.