Method for forming an IC including a varactor with reduced surface field region

A method for forming a varactor, the method comprising:

• forming a gate structure over a substrate;
• forming a well region having a first doping type within the substrate and underlying the gate structure;
• forming a reduced surface field (RESURF) region having a second doping type within the substrate and underlying the well region, wherein the RESURF region contacts the well region at a PN-junction, wherein the first doping type is opposite the second doping type;
• and
• forming a pair of contact regions within the well region and on opposing sides of the gate structure, wherein the pair of contact regions comprise the first doping type, wherein a doping concentration of the pair of contact regions is greater than a doping concentration of the well region, wherein a top surface of the well region is vertically aligned with a top surface of the pair of contact regions.

A method for forming an integrated circuit (IC), the method comprising:

• forming an isolation structure into a top surface of a substrate;
• forming a gate structure over the substrate, wherein the gate structure is spaced laterally between a first sidewall of the isolation structure and a second sidewall of the isolation structure;
• forming a drift region having a first doping type within the substrate;
• forming a reduced surface field (RESURF) region having a second doping type within the substrate and along a bottom surface of the drift region, wherein the drift region and the RESURF region respectively continuously laterally extend from the first sidewall to the second sidewall;
• and
• forming a pair of contact regions having the first doping type within the drift region and on opposing sides of the gate structure, wherein the first doping type is opposite the second doping type.