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US 11,978,799 B2Granted
Method for fabricating transistor with thinned channel
AssigneeTahoe Research, Ltd.
InventorsJustin K. Brask, Robert S. Chau, Suman Datta, Mark L. Doczy, Brian S. Doyle, Jack T. Kavalieros, Amlan Majumdar, Matthew V. Metz, Marko Radosavljevic
Life of this patent
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Abstract
A method of fabricating a MOS transistor having a thinned channel region is described. The channel region is etched following removal of a dummy gate. The source and drain regions have relatively low resistance with the process.
Claims26
An apparatus comprising:
- a processor;
- and
- a network interface coupled to the processor via a bus, wherein the processor includes a non-planar transistor comprising:
- a gate electrode comprising a tri-gate structure;
- a semiconductor body;
- a gate dielectric between the gate electrode and the semiconductor body;
- a dielectric layer spaced from the gate dielectric;
- and
- a spacer that abuts the dielectric layer and the gate dielectric to space the dielectric layer from the gate dielectric, the gate dielectric being positioned between the gate electrode and the spacer.
6 more elements
An apparatus comprising:
- a processor;
- and
- a network interface coupled to the processor via a bus, wherein the processor includes a non-planar transistor comprising:
- a gate electrode comprising a tri-gate structure;
- a semiconductor body;
- a gate dielectric between the gate electrode and the semiconductor body;
- a dielectric layer spaced from the gate dielectric;
- and
- a spacer that abuts the dielectric layer and the gate dielectric to space the dielectric layer from the gate dielectric, wherein the gate dielectric is between the gate electrode and the semiconductor body, the gate electrode and the spacer, and the gate electrode and another spacer.
6 more elements
A method for forming a non-planar transistor, the method comprising:
- forming a gate electrode comprising a tri-gate structure;
- forming a three-dimensional semiconductor body;
- forming a gate dielectric between the gate electrode and the three-dimensional semiconductor body;
- forming a spacer;
- and
- forming a dielectric layer spaced from the gate dielectric, wherein the spacer abuts the dielectric layer and the gate dielectric to space the dielectric layer from the gate dielectric, the gate dielectric being positioned between the gate electrode and the spacer.
3 more elements
A non-planar transistor comprising:
- a gate electrode comprising a tri-gate structure;
- a three-dimensional semiconductor body;
- a gate dielectric between the gate electrode and the three-dimensional semiconductor body;
- a dielectric layer spaced from the gate dielectric;
- and
- a spacer that abuts the dielectric layer and the gate dielectric to space the dielectric layer from the gate dielectric, the gate dielectric being positioned between the gate electrode and the spacer.
3 more elements
An apparatus comprising:
- a processor;
- and
- a network interface coupled to the processor via a bus, wherein the processor includes a non-planar transistor comprising:
- a gate electrode comprising a tri-gate structure;
- a semiconductor body;
- a gate dielectric between the gate electrode and the semiconductor body;
- a dielectric layer spaced from the gate dielectric;
- and
- a spacer that abuts the dielectric layer and the gate dielectric to space the dielectric layer from the gate dielectric, wherein the entire spacer is spaced from the gate electrode.
6 more elements
Dependencies are inferred from the claim text.