High voltage field effect transistor with vertical current paths and method of making the same

A semiconductor structure comprising:

• a shallow trench isolation structure comprising a dielectric material embedded within a semiconductor material layer and laterally surrounding an upper portion of the semiconductor material layer, wherein the upper portion of the semiconductor material layer comprises a base semiconductor portion comprising a pair of top horizontal surfaces and a pedestal semiconductor portion located between the pair of top horizontal surfaces and vertically protruding above a horizontal plane including the pair of top horizontal surfaces;
• a gate stack structure comprising a gate dielectric and a gate electrode and including a pair of sidewalls that are vertically coincident with a pair of sidewalls of the pedestal semiconductor portion;
• a dielectric gate spacer contacting the pair of sidewalls of the gate stack structure and the pair of sidewalls of the pedestal semiconductor portion;
• a source region and a drain region located within the base semiconductor portion and having a respective top surface located within the horizontal plane including the pair of top horizontal surfaces of the base semiconductor portion;
• a dielectric liner continuously extending over and contacting a top surface of the source region, a top surface of the drain region, an outer sidewall of the dielectric gate spacer, and a top surface of the gate stack structure;
• a planarization dielectric layer overlying the dielectric liner and having a planar top surface;
• contact via structures vertically extending through the planarization dielectric layer and the dielectric liner and contacting a respective one of the source region, the drain region, and the gate electrode;
• and
• a doped extension region in contact with a respective sidewall of the pair of sidewalls of the pedestal semiconductor portion, adjoined to a respective one of the source region and the drain region, having a same type of doping as the source region and the drain region, and including dopants at a lower atomic concentration than the source region and the drain region,
• wherein:
• a first portion of the base semiconductor portion and a first portion of the pedestal semiconductor portion has a doping of a first conductivity type;
• the source region, the drain region, and the doped extension region have a doping of a second conductivity type that is opposite to the first conductivity type;
• and
• a p-n junction between a combination of the first portion of the base semiconductor portion and the first portion of the pedestal semiconductor portion, and a combination of the doped extension region and the respective one of the source region and the drain region comprises a horizontally-extending surface of the first portion of the base semiconductor portion that contacts the respective one of the source region and the drain region and further comprises a vertically-extending surface of the first portion of the pedestal semiconductor portion that contacts the doped extension region.

A semiconductor structure comprising:

• a shallow trench isolation structure comprising a dielectric material embedded within a semiconductor material layer and laterally surrounding an upper portion of the semiconductor material layer, wherein the upper portion of the semiconductor material layer comprises a base semiconductor portion comprising a pair of top horizontal surfaces and a pedestal semiconductor portion located between the pair of top horizontal surfaces and vertically protruding above a horizontal plane including the pair of top horizontal surfaces;
• a gate stack structure comprising a gate dielectric and a gate electrode and including a pair of sidewalls that are vertically coincident with a pair of sidewalls of the pedestal semiconductor portion;
• a dielectric gate spacer contacting the pair of sidewalls of the gate stack structure and the pair of sidewalls of the pedestal semiconductor portion;
• and
• a source region and a drain region located within the base semiconductor portion and having a respective top surface located within the horizontal plane including the pair of top horizontal surfaces of the base semiconductor portion;
• wherein:
• the base semiconductor portion comprises a first single crystalline semiconductor material portion having a doping of the first conductivity type;
• the source region and the drain region have a doping of a second conductivity type that is an opposite of the first conductivity type;
• the pedestal semiconductor portion comprises of a second single crystalline semiconductor material potion having a doping of the first conductivity type and a doped extension region having a doping of the second conductivity type and adjoined to a respective one of the source region and the drain region and including dopants at a lower atomic concentration than the source region and the drain region;
• and
• a p-n junction between a combination of the first portion of the first single crystalline semiconductor material portion and the second single crystalline semiconductor material potion, and a combination of the doped extension region and the respective one of the source region and the drain region comprises a horizontally-extending surface of the first single crystalline semiconductor material portion that contacts the respective one of the source region and the drain region and further comprises a vertically-extending surface of the second single crystalline semiconductor material potion that contacts the doped extension region.