Page buffer circuit and memory device including the same

A memory device comprising:

• a first semiconductor layer including a plurality of memory cells respectively connected to a plurality of bit lines extending in a first horizontal direction;
• and
• a second semiconductor layer provided in a vertical direction that is perpendicular to the first semiconductor layer, the second semiconductor layer including a plurality of page buffers,
• wherein the plurality of page buffers comprises a first page buffer unit including a first sensing node and a second page buffer unit including a second sensing node,
• wherein the first sensing node comprises:
• a first lower metal pattern provided in a lower metal layer;
• and
• a first upper metal pattern provided in an upper metal layer provided above the lower metal layer in the vertical direction, and electrically connected to the lower metal pattern,
• wherein the second sensing node comprises:
• a second lower metal pattern provided in the lower metal layer;
• and
• a second upper metal pattern provided in the upper metal layer,
• wherein the second page buffer unit is provided adjacent to the first page buffer unit in a second horizontal direction, and
• wherein the first upper metal pattern is not adjacent to the second upper metal pattern in the second horizontal direction.

A memory device comprising:

• a memory cell region including a plurality of memory cells and a first metal pad;
• and
• a peripheral circuit region including a second metal pad and connected to the memory cell region in a vertical direction through the first metal pad and the second metal pad,
• wherein the peripheral circuit region further includes a plurality of page buffers,
• wherein the plurality of page buffers comprises a first page buffer unit including a first sensing node and a second page buffer unit including a second sensing node,
• wherein the first sensing node comprises:
• a first lower metal pattern provided in a lower metal layer;
• and
• a first upper metal pattern provided in an upper metal layer provided above the lower metal layer in the vertical direction, and electrically connected to the lower metal pattern,
• wherein the second sensing node comprises:
• a second lower metal pattern provided in the lower metal layer;
• and
• a second upper metal pattern provided in the upper metal layer,
• wherein the second page buffer unit is provided adjacent to the first page buffer unit in a second horizontal direction, and
• wherein the first upper metal pattern is not adjacent to the second upper metal pattern in the second horizontal direction.