Multi-reset and multi-clock synchronizer, and synchronous multi-cycle reset synchronization circuit
AssigneeIntel Corporation
InventorsLeon Zlotnik, Lev Zlotnik, Jeremy Anderson
Life of this patent
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Abstract
An asynchronous multi-cycle reset synchronization circuit that can correlate any number of resets and synchronous clocks with simultaneous reset de-assertion and removal of reset assertion crossing hazards. The asynchronous multi-cycle reset synchronization circuit can also be paired with a synchronous multi-cycle reset synchronization circuit to correlate same domain asynchronous and synchronous resets. Also described is a synchronous reset multi-cycle synchronization circuit that correlates with any number of asynchronous resets and guarantees simultaneous reset de-assertion.
Claims23
An apparatus comprising:
- a first synchronizer circuit comprising at least two sequential circuits coupled in series, wherein the first synchronizer circuit is to pass a reset to a clock gate;
- and
- a second synchronizer circuit comprising at least two sequential circuits, wherein the second synchronizer circuit is to substantially eliminate a possible glitch from the reset, and to provide at least two clock cycle relaxation to propagation of de-assertion of the reset.
An apparatus comprising:
- a first synchronizer circuit comprising at least two sequential circuits coupled in series, wherein the first synchronizer circuit is to pass a reset to a clock gate;
- a second synchronizer circuit comprising a sequential circuit, wherein the second synchronizer circuit is to substantially eliminate a possible glitch from the reset, and to provide at least two clock cycle relaxation to propagation of de-assertion of the reset;
- and
- at least one buffer coupled between the first synchronizer and the second synchronizer.
An apparatus comprising:
- a first circuitry comprising a multi-reset and multi-clock synchronizer;
- and
- a second circuitry coupled to the first circuitry, wherein the first circuitry is to receive a first clock having a first frequency, wherein the second circuitry is to receive a second clock having a second frequency, wherein the second frequency is slower than the first frequency, wherein the first and second circuitries are to receive an input reset, and wherein the second circuitry comprises a multi-reset and multi-clock synchronizer, wherein the first circuitry comprises (i) a first synchronizer circuit comprising at least two sequential circuits coupled in series, wherein the first synchronizer circuit is to pass reset to a clock gate, and (ii) a second synchronizer circuit comprising at least two sequential circuits, wherein the second synchronizer circuit is to substantially eliminate a possible glitch from the reset, and to provide at least two clock cycle relaxation to propagation of de-assertion of the reset.
A system comprising:
- a memory;
- a processor coupled to the memory;
- and
- a wireless interface to allow the processor to communicate with another device, wherein the processor includes an apparatus that includes:
- a first synchronizer circuit comprising at least two sequential circuits coupled in series, wherein the first synchronizer circuit is to pass a reset to a clock gate;
- and
- a second synchronizer circuit comprising at least two sequential circuits, wherein the second synchronizer circuit is to substantially eliminate a possible glitch from the reset, and to provide at least two clock cycle relaxation to propagation of de-assertion of the reset.
Dependencies are inferred from the claim text.