Staggered word line architecture for reduced disturb in 3-dimensional nor memory arrays
AssigneeSunrise Memory Corporation
InventorScott Brad Herner
Life of this patent
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Abstract
A staggered memory cell architecture staggers memory cells on opposite sides of a shared bit line preserves memory cell density, while increasing the distance between such memory cells, thereby reducing the possibility of a disturb. In one implementation, the memory cells along a first side of a shared bit line are connected to a set of global word lines provided underneath the memory structure, while the memory cells on the other side of the shared bit line—which are staggered relative to the memory cells on the first side—are connected to global word lines above the memory structure.
Claims33
A memory structure comprising a plurality of NOR memory strings form above a planar surface of a substrate, wherein each NOR memory string comprises a plurality of memory cells sharing a common bit line and a common source line, wherein (i) each memory cell is associated with a gate electrode, (ii) the common bit line extends lengthwise along a first direction substantially parallel the planar surface, (iii) a first group of the memory cells are formed along a first side of the common bit line and (iv) a second group of the memory cells are formed along a second side of the common bit line opposite the first side, and (v) the gate electrodes of the memory cells on the first side and the gate electrodes of the memory cells on the second side are provided in a staggered configuration.
A NOR memory string, comprising:
- a bit line having a length that extends along a first direction;
- a source line, and
- a plurality of memory cells formed along a first side and a second side of the bit line, the first and the second sides of the bit line being opposite each other along the length of the bit line, each memory cell comprising (i) a channel region adjacent to both the bit line and the source line;
- and (ii) a gate electrode having a length extending along a second direction substantially orthogonal to the first direction;
- wherein (i) the gate electrodes of the memory cells along the first side of the bit line and the gate electrodes of the memory cells along the second side of the bit line are provided in a staggered configuration;
- and (ii) the first conductive layer and the second conductive layer are separated from each other substantially uniformly by a distance along the first direction.
An array of NOR memory strings, wherein each NOR memory string comprises:
- a bit line having a length that extends along a first direction;
- a source line, and
- a plurality of memory cells formed along a first side and a second side of the bit line, the first and the second sides of the bit line being opposite each other along the length of the bit line, each memory cell comprising (i) a channel region adjacent to both the bit line and the source line;
- and (ii) a gate electrode having a length extending along a second direction substantially orthogonal to the first direction;
- wherein (i) the gate electrodes of the memory cells along the first side of the bit line and the gate electrodes of the memory cells along the second side of the bit line are provided in a staggered configuration;
- (ii) the first conductive layer and the second conductive layer are separated from each other substantially uniformly by a distance along the first direction;
- and (iii) the array of NOR memory strings is formed above a planar surface of a substrate.
Dependencies are inferred from the claim text.