Oscillation system including frequency-locked loop logic circuit and operating method thereof

An oscillation system comprising:

• a relaxation oscillator;
• and
• a frequency-locked loop (FLL) logic circuit coupled to the relaxation oscillator, wherein the FLL logic circuit includes:
• a validity signal generator configured to receive an external clock signal and determine whether there is a glitch in the external clock signal,
• a clock divider configured to generate a reference frequency clock signal based on the external clock signal and a determination result of the validity signal generator,
• a synchronizer configured to synchronize a phase of an oscillator clock signal with a phase of the reference frequency clock signal,
• a clock counter coupled to the synchronizer and configured to count a number of pulses of the oscillator clock signal for a reference time, and
• a code limiter configured to determine a range of a frequency selection value for calibrating an operating frequency of the oscillator clock signal based on the counted number of pulses.

An operating method of a frequency-locked loop (FLL) logic circuit, the operating method comprising:

• receiving an external clock signal;
• determining whether a glitch occurs in the external clock signal;
• generating a reference frequency clock signal based on determining that the glitch does not occur in the external clock signal;
• synchronizing a phase of the reference frequency clock signal with a phase of an oscillator clock signal;
• performing clock counting;
• determining whether an operating frequency of the oscillator clock signal is identical to a target frequency based on a result of the clock counting;
• and
• adjusting a frequency selection value based on the result of the clock counting,
• wherein the frequency selection value is used to calibrate the operating frequency of the oscillator clock signal.