Ternary in-memory accelerator

A circuit of cells used as a memory array and capable of in-memory arithmetic, comprising:

• a plurality of signed ternary processing cells each having a first bitline and a second bitline and coupled to each other in a parallel fashion such that the first bitlines of the plurality of signed ternary processing cells are coupled to each other and the second bitlines of the plurality of signed ternary processing cells are coupled to each other, each signed ternary processing cell comprising:
• a first memory cell, adapted to hold a first digital value;
• a second memory cell, adapted to hold a second digital value, wherein a binary combination of the first digital value and the second digital value establishes a first signed ternary operand;
• a signed ternary input forming a second signed ternary operand;
• and
• a signed ternary output, wherein the signed ternary output represents a signed multiplication of the first signed ternary operand and the second signed ternary operand by voltage changes in the first and second bitlines;
• a sense circuit adapted to (a) receive the coupled first and second bitlines of the plurality of signed ternary processing cells, (b) compute the difference between the values represented by the coupled first bitlines and the coupled second bitlines, and (c) output a subtraction result, wherein each signed ternary processing cell further comprising:
• a first bitline coupled to the first memory cell;
• a second bitline coupled to the second memory cell;
• a first read wordline;
• and
• a second read wordline, wherein the multiplication of the first signed ternary operand and the second signed ternary operand is generated by (a) precharging the first and second bitlines, (b) selectively and temporarily activating the first and second read wordlines, and (c) comparing the first and second bitlines and inferring the multiplication output based on the comparison results.