Rram structure
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsHai-Dang Trinh, Chii-Ming Wu, Hsing-Lien Lin, Fa-Shen Jiang
Life of this patent
Estimating the term…
Abstract
In some embodiments, the present disclosure relates to an integrated chip. The integrated chip includes a bottom electrode disposed over one or more interconnects and a diffusion barrier layer on the bottom electrode. The diffusion barrier layer has an inner upper surface that is arranged laterally between and vertically below an outer upper surface of the diffusion barrier film. The outer upper surface wraps around the inner upper surface in a top-view of the diffusion barrier layer. A data storage structure is separated from the bottom electrode by the diffusion barrier layer. A top electrode is arranged over the data storage structure.
Claims20
An integrated chip, comprising:
- a first conductive structure disposed on a first interconnect within a dielectric structure on a substrate;
- a diffusion barrier on the first conductive structure;
- a data storage structure on the diffusion barrier;
- a second conductive structure on the data storage structure;
- a dielectric spacer disposed along sidewalls and an upper surface of the second conductive structure;
- an insulating layer disposed along sidewalls and an upper surface of the dielectric spacer, the insulating layer vertically extending from below a bottom of the dielectric spacer to over a top of the dielectric spacer;
- a second interconnect extending through the dielectric spacer and the insulating layer to contact the second conductive structure;
- a first access device comprising a first gate structure disposed on the substrate between a first source region and a common drain;
- and
- a second access device comprising a second gate structure disposed on the substrate between a second source region and the common drain, wherein the first interconnect is electrically coupled to the common drain.
An integrated chip, comprising:
- a lower electrode disposed on a first interconnect within a lower inter-level dielectric (ILD) layer over a substrate;
- a data storage structure over the lower electrode;
- a metal diffusion barrier separating the lower electrode from the data storage structure;
- an upper electrode on the data storage structure;
- a dielectric spacer disposed along an upper surface of the upper electrode and along sidewalls of the upper electrode and the data storage structure;
- an insulating layer disposed along sidewalls and an upper surface of the dielectric spacer, the insulating layer vertically extending from below a bottom of the dielectric spacer to over a top of the dielectric spacer;
- a second ILD layer laterally surrounding the insulating layer;
- and
- a second interconnect contacting the upper electrode.
An integrated chip, comprising:
- an inert metal lower electrode disposed on a first interconnect over a substrate;
- a metal diffusion barrier on the inert metal lower electrode;
- a data storage structure on the metal diffusion barrier;
- a metal upper electrode on the data storage structure;
- a dielectric spacer disposed along sidewalls and an upper surface of the metal upper electrode;
- an insulating layer disposed along sidewalls and an upper surface of the dielectric spacer, the insulating layer vertically extending from below a bottom of the dielectric spacer to over a top of the dielectric spacer;
- and
- a second interconnect extending through the dielectric spacer and the insulating layer to contact the metal upper electrode.
Dependencies are inferred from the claim text.