Method for manufacturing memory device having resistance switching layer
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsHsin-Hsiang Tseng, Chih-Lin Wang, Yi-Huang Wu
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Abstract
A method for manufacturing a memory device is provided. The method includes etching an opening in a first dielectric layer; forming a bottom electrode, a resistance switching element, and a top electrode in the opening in the first dielectric layer; forming a second dielectric layer over the bottom electrode, the resistance switching element, and the top electrode; and forming an electrode via connected to a top surface of the top electrode in the second dielectric layer.
Claims20
A method for manufacturing a memory device, the method comprising:
- etching an opening in a first dielectric layer;
- forming a bottom electrode, a resistance switching element, and a top electrode in the opening in the first dielectric layer, wherein the top electrode is surrounded by the resistance switching element in a top view;
- forming a second dielectric layer over the bottom electrode, the resistance switching element, and the top electrode;
- and
- forming an electrode via connected to a top surface of the top electrode in the second dielectric layer.
A method for manufacturing a memory device, the method comprising:
- depositing a bottom electrode layer;
- depositing a resistance switching layer over the bottom electrode layer, wherein the resistance switching layer has a first portion in a recess in the bottom electrode layer and a second portion external to the recess in the bottom electrode layer;
- depositing a top electrode layer over the resistance switching layer to fill the recess in the bottom electrode layer;
- and
- performing a planarization process to the bottom electrode layer, the resistance switching layer, and the top electrode layer.
A method for manufacturing a memory device, the method comprising:
- forming a conductive feature over a substrate;
- depositing a dielectric layer over the conductive feature;
- etching a first opening in the dielectric layer over the conductive feature;
- forming a spacer on a sidewall of the first opening of the dielectric layer, wherein the spacer forms a closed loop around the conductive feature when viewed from top;
- and
- forming a bottom electrode, a resistance switching element, and a top electrode in the first opening in the dielectric layer, wherein the spacer surrounds the bottom electrode, the resistance switching element, and the top electrode.
Dependencies are inferred from the claim text.