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US 11,963,456 B2Granted
MRAM memory array yield improvement
AssigneeInternational Business Machines Corporation
InventorsDimitri Houssameddine, Kangguo Cheng, Julien Frougier, Ruilong Xie
Life of this patent
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Abstract
Embodiments of present invention provide a method of improving yield of making MRAM arrays. More specifically, the method includes receiving an MRAM array; identifying a weak MRAM cell from the MRAM array wherein the weak MRAM cell includes an access transistor; and modifying the access transistor. In one embodiment, modifying the access transistor includes performing a hot carrier injection into a gate dielectric layer of the access transistor.
Claims20
A method comprising:
- receiving a magnetoresistive random-access memory (MRAM) array;
- identifying a weak MRAM cell from the MRAM array, wherein the weak MRAM cell comprises an access transistor, and
- modifying the access transistor.
A method comprising:
- receiving a magnetoresistive random-access memory (MRAM) device;
- identifying at least one weak MRAM cell from the MRAM device, wherein the at least one weak MRAM cell comprises an access transistor and a magnetic tunnel junction (MTJ) connected to a drain of the access transistor;
- a word line connected to a gate of the access transistor;
- a source line connected to a source of the access transistor;
- and a bit line connected to the drain of the access transistor via the MTJ, and
- modifying the access transistor.
3 more elements
A magnetoresistive random-access memory (MRAM) device comprising:
- an array of MRAM cells of M columns and N rows wherein M and N are individually equal to or larger than 5;
- each MRAM cell includes an access transistor that has a threshold voltage,
- wherein at least one of the MRAM cells has a threshold voltage that is lower by about 0.05V than an average of the threshold voltage of rest of the MRAM cells.
Dependencies are inferred from the claim text.