Array substrate and display device

An array substrate, comprising:

• a base substrate, comprising a display region and a peripheral region surrounding the display region, the display region comprising a first boundary, a second boundary, a third boundary and a fourth boundary;
• a plurality of sub-pixels, in the display region, at least one of the sub-pixels comprising a light-emitting element, and the light-emitting element comprising a first electrode, a light-emitting layer and a second electrode which are stacked;
• a plurality of positive power lines, in the display region and electrically connected to the plurality of sub-pixels;
• a positive power bus, in the peripheral region and extending along the first boundary, the positive power bus being electrically connected to the plurality of positive power lines;
• a first positive power access end, a second positive power access end and a third positive power access end, in a portion of the peripheral region at a side of the positive power bus away from the display region, the second positive power access end being between the first positive power access end and the third positive power access end, and the first positive power access end, the second positive power access end and the third positive power access end being respectively and electrically connected to the positive power bus;
• a negative power line, in the peripheral region and surrounding the second boundary, the third boundary and the fourth boundary;
• an auxiliary electrode, in the peripheral region and surrounding the first boundary, the second boundary, the third boundary and the fourth boundary, the auxiliary electrode being respectively and electrically connected to the negative power line and the second electrode;
• a first negative power access end, a second negative power access end, a third negative power access end and a fourth negative power access end, in the portion of the peripheral region at the side of the positive power bus away from the display region, the first negative power access end being at a side of the first positive power access end away from the second positive power access end, the second negative power access end being between the first positive power access end and the third positive power access end, the third negative power access end being at a side of the third positive power access end away from the second positive power access end, the fourth negative power access end being between the second negative power access end and the third positive power access end, and the first negative power access end and the third negative power access end being respectively and electrically connected to the negative power line;
• and
• a negative power auxiliary line, in the peripheral region, between the second negative power access end and the fourth negative power access end in a first direction, and between the positive power bus and the second negative power access end in a second direction, one end of the negative power auxiliary line is connected to the second negative power access end, another end of the negative power auxiliary line is connected to the fourth negative power access end, and the first direction intersecting with the second direction;
• wherein the negative power auxiliary line is electrically connected to the auxiliary electrode, and an orthographic projection of the negative power auxiliary line on the base substrate at least partially overlaps with an orthographic projection of the auxiliary electrode on the base substrate.