Three-terminal electro-chemical memory cell with vertical structure for neuromorphic computation and memory cell array including the same
AssigneeSeoul National University R&Db Foundation
InventorsYun Seog Lee, Hyunjoon Lee
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Abstract
Disclosed is a three-terminal electro-chemical memory cell with a vertical structure for neuromorphic computation, including a circumferential hole, first and second conductive electrode layers sequentially stacked along an outer surface of the circumferential hole, an electrolyte layer formed along an inner surface of the circumferential hole and connected to one end of each of the first and second conductive electrode layers, and a gate electrode disposed parallel to the electrolyte layer in an inner surface direction of the circumferential hole.
Claims12
A three-terminal electro-chemical memory device with a vertical structure for neuromorphic computation, comprising:
- a circumferential hole;
- first and second conductive electrode layers sequentially stacked along an outer surface of the circumferential hole;
- an electrolyte layer formed along an inner surface of the circumferential hole and connected to one end of each of the first and second conductive electrode layers;
- a gate electrode layer disposed parallel to the electrolyte layer in an inner surface direction of the circumferential hole;
- and
- an insulator filled in an inner surface of the gate electrode layer.
A three-terminal electro-chemical memory cell with a vertical structure for neuromorphic computation, comprising:
- a circumferential hole;
- first and second conductive electrode layers sequentially stacked along an outer surface of the circumferential hole;
- a channel layer formed along an inner surface of the circumferential hole and connected to one end of each of the first and second conductive electrode layers;
- and
- a gate electrode layer disposed parallel to the channel layer in an inner surface direction of the circumferential hole;
- and
- an insulator filled in an inner surface of the gate electrode layer.
A circumferential three-terminal memory cell with a vertical structure for neuromorphic computation, comprising:
- a channel layer, an electrolyte layer, and a gate electrode layer sequentially forming a circumferential surface toward an inside;
- first and second conductive electrode layers sequentially stacked in a disk shape on an outside of the circumferential surface;
- and
- an insulator filled in an inner surface of the gate electrode layer.
An array of three-terminal memory cell with a vertical structure for neuromorphic computation, comprising:
- a channel layer, an electrolyte layer, and a gate electrode layer sequentially forming a circumferential surface toward an inside;
- first and second conductive electrode layers sequentially stacked in a disk shape on an outside of the circumferential surface;
- a drain line connected to the first conductive electrode layer;
- a source line connected to the second conductive electrode layer;
- a gate line connected to the gate electrode layer;
- and
- an insulator filled in an inner surface of the gate electrode layer.
Dependencies are inferred from the claim text.