US 11,963,369 B2 · Memory array with asymmetric bit-line architecture

Abstract

The present disclosure relates to an integrated circuit. The integrated circuit has a plurality of bit-line stacks disposed over a substrate and respectively including a plurality of bit-lines stacked onto one another. A data storage structure is over the plurality of bit-line stacks and a selector is over the data storage structure. A word-line is over the selector. The selector is configured to selectively allow current to pass between the plurality of bit-lines and the word-line. The plurality of bit-line stacks include a first bit-line stack, a second bit-line stack, and a third bit-line stack. The first and third bit-line stacks are closest bit-line stacks to opposing sides of the second bit-line stack. The second bit-line stack is separated from the first bit-line stack by a first distance and is further separated from the third bit-line stack by a second distance larger than the first distance.

Claims20

Dependent claims

An integrated circuit, comprising:

a plurality of bit-line stacks disposed over a substrate and respectively comprising a plurality of bit-lines stacked onto one another;
a data storage structure over the plurality of bit-line stacks;
a selector over the data storage structure;
a word-line over the selector, wherein the selector is configured to selectively allow current to pass between the plurality of bit-lines and the word-line;
wherein the plurality of bit-line stacks comprise a first bit-line stack, a second bit-line stack, and a third bit-line stack, the first bit-line stack and the third bit-line stack are closest bit-line stacks to opposing sides of the second bit-line stack;
and
wherein the second bit-line stack is separated from the first bit-line stack by a first distance and is further separated from the third bit-line stack by a second distance larger than the first distance.

4 more elements

Dependencies are inferred from the claim text.

Memory array with asymmetric bit-line architecture

Life of this patent

Memory array with asymmetric bit-line architecture

Life of this patent

Abstract

Claims20