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US 11,963,368 B2Granted
Resistive random access memory device
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsChun-Chieh Mo, Shih-Chi Kuo, Tsai-Hao Hung
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Abstract
A memory includes: a dielectric fin formed over a substrate; and a pair of memory cells disposed along respective sidewalls of the dielectric fin, each of the pair of memory cells comprising: a first conductor layer; a selector layer; a resistive material layer; and a second conductor layer, wherein the first conductor layer, selector layer, resistive material layer, and second conductor layer each includes upper and lower boundaries, and at least one of the upper and lower boundaries is tilted away from one of the sidewalls of the dielectric fin by an angle.
Claims20
A memory device, comprising:
- a dielectric fin formed over a substrate;
- a memory cell disposed along and directly contacting a flat surface of a first sidewall of the dielectric fin, the memory cell comprising:
- a first conductor layer, a selector layer, a resistive material layer, and a second-conductor layer, wherein each of the first conductor layer, the selector layer, the resistive material layer, and the second conductor layer directly contact the first sidewall, wherein lower and upper boundaries of the selector layer are each tilted away from the flat surface by an angle, wherein the angle is less than 90 degrees;
- and
- a capping layer disposed along and directly contacting each of the first conductor layer, the selector layer, the resistive material layer, and the second conductor layer such that the memory cell is disposed directly between the capping layer and the dielectric fin.
2 more elements
A memory device, comprising:
- a plurality of dielectric fins formed over a substrate;
- and
- a plurality of memory cells disposed along respective sidewalls of the plurality of dielectric fins, each memory cells comprising:
- a first conductor layer, a selector layer;
- a resistive material layer, and a second conductor layer, wherein each of the first conductor layer, the selector layer, the resistive material layer and the second conductor layer of each memory cell directly contacts a respective flat surface of a respective sidewall of a respective dielectric fin, wherein lower and upper boundaries of the selector layer are each tilted away from the respective flat surface by an angle, wherein the angle is less than 90 degrees;
- and
- a capping layer disposed along and directly contacting each of the first conductor layer, the selector layer, the resistive material layer, and the second conductor layer such that the at least one memory cell is disposed directly between the capping layer and a respective dielectric fin of the plurality of dielectric fins.
4 more elements
A memory device, comprising:
- a dielectric fin formed over a substrate, the dielectric fin having a first side surface and a second side surface opposite the first side surface;
- a first memory cell disposed along and directly contacting a first flat surface of the first side surface of the dielectric fin, the first memory cell comprising:
- a first lower conductor layer, a first selector layer, a first resistive material layer, and a first upper conductor layer, wherein each of the first lower conductor layer, the first selector layer, the first resistive material layer, and the first upper conductor layer directly contact the first flat surface of the first side surface, wherein lower and upper boundaries of the first selector layer are each tilted away from the first flat surface by an angle, wherein the angle is less than 90 degrees;
- and
- a second memory cell disposed along and directly contacting a second flat surface of the second side surface of the dielectric fin, the second memory cell comprising:
- a second lower conductor layer, a second selector layer, a second resistive material layer, and a second upper conductor layer, wherein each of the second lower conductor layer, the second selector layer, the second resistive material layer, and the second upper conductor layer directly contact the second flat surface of the second side surface;
- and
- a capping layer disposed along and directly contacting each of the first lower conductor layer, the selector layer, the resistive material layer, and the first upper conductor layer such that the first memory cell is disposed directly between the capping layer and the dielectric fin.
5 more elements
Dependencies are inferred from the claim text.