Back-end active device, semiconductor device and semiconductor chip

A semiconductor device, comprising:

• active devices, respectively comprising:
• a first channel layer;
• a first top source/drain electrode, disposed at a top side of the first channel layer;
• a first bottom source/drain electrode and a second bottom source/drain electrode, disposed at a bottom side of the first channel layer;
• a first gate structure and a second gate structure, located between the first top source/drain electrode and the first bottom source/drain electrode, wherein the first gate structure comprises a non-ferroelectric dielectric layer, and the second gate structure comprises a ferroelectric layer;
• and
• a third gate structure and a fourth gate structure, located between the first top source/drain electrode and the second bottom source/drain electrode, wherein the third gate structure comprises a non-ferroelectric dielectric layer, and the fourth gate structure comprises a ferroelectric layer;
• memory cells, laterally adjacent to the active devices, and respectively comprise an access transistor and a storage element coupled to the access transistor.

A semiconductor chip, comprising:

• a substrate;
• a first active device, formed on the substrate;
• a stack of dielectric layers, formed over the substrate, wherein the first active device is covered by the stack of dielectric layers;
• and
• a second active device, embedded in the stack of dielectric layers, and comprising:
• a channel layer;
• a top source/drain electrode, disposed at a top side of the channel layer;
• a first bottom source/drain electrode and a second bottom source/drain electrode, disposed at a bottom side of the channel layer;
• a first gate structure and a second gate structure, located between the top source/drain electrode and the first bottom source/drain electrode, wherein the first gate structure comprises a non-ferroelectric dielectric layer, and the second gate structure comprises a ferroelectric layer;
• and
• a third gate structure and a fourth gate structure, located between the top source/drain electrode and the second bottom source/drain electrode, wherein the third gate structure comprises a non-ferroelectric dielectric layer, and the fourth gate structure comprises a ferroelectric layer.