Integrated circuit device including vertical memory device

An integrated circuit device, comprising:

• a substrate having a cell region, a peripheral circuit region, and an interconnection region between the cell region and the peripheral circuit region;
• and
• a plurality of stacks sequentially stacked on the substrate, wherein:
• each stack among the plurality of stacks includes a cell stack structure that has a plurality of insulating layers and a plurality of word line structures alternately stacked on the substrate in the cell region and the interconnection region,
• a stack among the plurality of stacks includes a dummy stack structure,
• the dummy stack structure is located at a same vertical level as one of the cell stack structures, except for a cell stack structure of a bottom stack among the plurality of stacks,
• the dummy stack structure is separate from the cell stack structures, and
• the dummy stack structure has a plurality of dummy insulating layers and a plurality of dummy support layers alternately stacked in the peripheral circuit region.

An integrated circuit device, comprising:

• a substrate having a cell region, a peripheral circuit region, and an interconnection region between the cell region and the peripheral circuit region;
• a first stack, the first stack including:
• a first cell stack structure including a plurality of first insulating layers and a plurality of first word line structures alternately stacked on the substrate in the cell region and the interconnection region,
• a first filling insulating layer in the interconnection region and the peripheral circuit region, and having an upper surface coplanar with an upper surface of a first cell mold structure, and
• a first protective insulating layer covering the first cell stack structure and the first filling insulating layer;
• and
• a second stack stacked on the first stack, the second stack including:
• a second cell stack structure including a plurality of second insulating layers and a plurality of second word line structures alternately stacked on the substrate in the cell region and the interconnection region,
• a dummy stack structure located at a same vertical level as the second cell stack structure, and including a plurality of dummy insulating layers and a plurality of dummy support layers alternately stacked in the peripheral circuit region,
• a second filling insulating layer in the interconnection region and the peripheral circuit region, the second filling insulating layer having an upper surface coplanar with an upper surface of the dummy stack structure, and being formed over a two-dimensionally wider area than the first filling insulating layer, and
• a second protective insulating layer covering the second cell stack structure, the dummy stack structure, and the second filling insulating layer,
• wherein a plurality of channel structures are in the cell region, the plurality of channel structures filling a plurality of first channel holes passing through the first stack, and filling a plurality of second channel holes respectively communicating with the plurality of first channel holes and passing through the second stack.