Three-dimensional memory device without gate line slits and method for forming the same

A three-dimensional (3D) memory device, comprising:

• a stack structure over a substrate and comprising a memory block comprising a plurality of memory cells;
• and
• a pair of dielectric select structures in the memory block, the dielectric select structures aligned with each other vertically, wherein:
• the substrate is configured to receive a source bias voltage.

A three-dimensional (3D) memory device, comprising:

• a stack structure comprising a plurality of conductor layers and a plurality of insulating layers interleaved over a substrate;
• a top select structure intersecting with a top conductor layer of the plurality of conductor layers in a memory block;
• a bottom select structure intersecting with a bottom conductor layer of the plurality of conductor layers and aligned with the top select structure vertically;
• and
• a plurality of channel structures extending vertically into the substrate and distributed in the memory block, wherein
• no array common source (ACS) is formed above the substrate.