Semiconductor memory device and manufacturing method thereof
AssigneeSK hynix Inc.
InventorDong Hwan Lee
Life of this patent
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Abstract
There are provided a semiconductor memory device and a manufacturing method thereof. The semiconductor memory device includes: a gate stack structure including interlayer insulating layers and conductive patterns, which are alternately stacked in a vertical direction on a substrate; a plurality of channel structures penetrating the gate stack structure, each of the plurality of channel structures with one end portion protruding past a boundary of the gate stack structure; and a source layer formed on the gate stack structure. The protruding end portion of each of the plurality of channel structures extends into the source layer. The protruding end portion of each of the plurality of channel structures has a flat section.
Claims11
A method of manufacturing a semiconductor memory device, the method comprising:
- forming a memory cell array on a first substrate, wherein the memory cell array includes:
- a gate stack structure with interlayer insulating layers and conductive patterns, which are alternately stacked in a vertical direction,
- a plurality of channel structures penetrating the gate stack structure, the plurality of channel structures each with an end portion extending into the first substrate, and
- a memory layer extending from between the plurality of channel structures and the gate stack structure to between the end portion of each of the plurality of channel structures and the first substrate;
- removing the first substrate to expose the memory layer;
- forming a first source layer on the top of the entire structure including the memory layer;
- performing an etching process to expose and level the memory layer, the channel structure, and the first source layer to be at the same height;
- and
- forming a second source layer on the memory layer, the channel structure, and the first source layer.
A method of manufacturing a semiconductor memory device, the method comprising:
- forming a memory cell array on a first substrate, wherein the memory cell array includes:
- a gate stack structure with interlayer insulating layers and conductive patterns, which are alternately stacked in a vertical direction,
- a plurality of channel structures penetrating the gate stack structure, the plurality of channel structures each with an end portion extending into the first substrate, and
- a memory layer extending from between the plurality of channel structures and the gate stack structure to between the end portion of each of the plurality of channel structures and the first substrate;
- forming a bit line that is connected to the memory cell array;
- removing the first substrate to expose the memory layer;
- forming a first source layer on the top of the entire structure including the memory layer;
- etching the first source layer, the memory layer, and the end portion of each of the plurality of channel structures by performing a Chemical Mechanical planarization (CMP) process;
- and
- forming a second source layer on the top of the entire structure that includes the first source layer, the memory layer, and the end portion of each of the plurality of channel structures, which are planarized.
Dependencies are inferred from the claim text.