US 11,963,348 B2 · Integrated circuit read only memory (ROM) structure

Abstract

A method of making a ROM structure includes the operations of forming an active area having a channel, a source region, and a drain region; depositing a gate electrode over the channel; depositing a conductive line over at least one of the source region and the drain region; adding dopants to the source region and the drain region of the active area; forming contacts to the gate electrode, the source region, and the drain; depositing a power rail, a bit line, and at least one word line of the integrated circuit against the contacts; and dividing the active area with a trench isolation structure to electrically isolate the gate electrode from the source region and the drain region.

Claims20

Dependent claims

A method of making an integrated circuit read only memory (ROM) structure, comprising:

forming a ROM transistor by
implanting an active area in a substrate to define a channel, a source region, and a drain region;
depositing a gate electrode over the channel;
removing a portion of the gate electrode and an underlying portion of the channel to form a trench separating a first portion of the active area and a second portion of the active area;
depositing a dielectric material to fill the trench and form a trench isolation structure to isolate the first portion of the active area from the second portion of the active area;
depositing a conductive line over at least one of the source region and the drain region;
adding dopants to the source region and the drain region of the active area;
forming a plurality of contacts comprising a gate electrode contact, a source region contact, and a drain region contact;
and
depositing a power rail, a bit line, and at least one word line of the integrated circuit over the contacts.

7 more elements

A method of manufacturing an integrated circuit structure, comprising:

forming a first drain contact;
forming a drain conductive line electrically connected to the first drain contact;
forming a first transistor comprising:
forming a first gate electrode,
forming a first gate electrode contact,
forming a first source,
forming a first source conductive line electrically connected to the first source,
forming a first source contact electrically connected to the first source conductive line,
forming a first drain electrically connected to the drain conductive line, and
forming a power rail electrically connected to the first source contact and a first gate electrode tie-off contact, wherein the first gate electrode tie-off contact electrically connects the power rail to the first gate electrode;
and
forming a second transistor comprising:
forming a second gate electrode,
forming a second gate electrode contact connected to the second gate electrode,
forming a second source,
forming a second source conductive line connected to the second source,
forming a second source contact connected to the second source conductive line and the power rail;
forming a second drain electrically connected to the drain conductive line;
and
forming a second gate electrode tie-off contact in electrical connection with both the second gate electrode and the power rail.

17 more elements

Dependencies are inferred from the claim text.

Integrated circuit read only memory (ROM) structure

Life of this patent

Integrated circuit read only memory (ROM) structure

Life of this patent

Abstract

Claims20