US 11,963,344 B2Granted

Integrated circuit device and manufacturing method thereof

AssigneeSamsung Electronics Co., Ltd.

InventorsJaybok Choi, Yongseok Ahn, Seunghyung Lee

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Abstract

A method of manufacturing an integrated circuit device includes: over a substrate, forming first hard mask patterns extending in a first direction parallel to a top surface of the substrate and arranged at a first pitch in a second direction; forming a plurality of first trenches in the substrate using the first hard mask patterns as etching masks; forming a plurality of first gate electrodes on inner walls of the plurality of first trenches; over the substrate, forming second hard mask patterns extending in the first direction and arranged at a second pitch in the second direction; forming a plurality of second trenches in the substrate using the second hard mask patterns as etching masks, each of the plurality of second trenches being disposed between two adjacent first trenches; and forming a plurality of second gate electrodes on inner walls of the plurality of second trenches.

Claims20

Dependent claims

An integrated circuit device comprising:

a substrate comprising a memory cell area;
a plurality of first gate electrodes in a plurality of first trenches in the memory cell area of the substrate and extending in a first direction parallel to a top surface of the substrate;
a plurality of second gate electrodes in a plurality of second trenches in the memory cell area of the substrate, the second gate electrodes extending in the first direction,
wherein the plurality of first gate electrodes alternate with the plurality of second gate electrodes in a second direction, the second direction parallel to the top surface of the substrate and perpendicular to the first direction,
a first end portion of each of the plurality of first gate electrodes is spaced apart from an edge of the memory cell area by a first distance, and
a second end portion of each of the plurality of second gate electrodes is spaced apart from the edge of the memory cell area by a second distance different from the first distance;
and
device isolation layers in the substrate, the device isolation layers defining a plurality of active layers,
wherein the plurality of first trenches comprise first portions vertically overlapping a plurality of active areas and second portions vertically overlapping the device isolation layers,
bottom surfaces of the first portions have a first depth from the top surface of the substrate, bottom surfaces of the second portions have a second depth greater than the first depth from the top surface of the substrate,
the plurality of second trenches comprise third portions vertically overlapping the plurality of active areas and fourth portions vertically overlapping the device isolation latyers,
bottom surfaces of the third portions have a third depth from the top surface of the substrate, and
bottom surfaces of the fourth portions have a fourth depth greater than the third depth from the top surface of the substrate.

10 more elements

An integrated circuit device comprising:

a plurality of first gate electrodes in a plurality of first trenches in a substrate, the plurality of first gate electrodes extending in a first direction parallel to a top surface of the substrate;
and
a plurality of second gate electrodes in a plurality of second trenches in the substrate, the plurality of second gate electrodes extending in the first direction,
wherein the plurality of first gate electrodes alternate with the plurality of second gate electrodes in a second direction, the second direction parallel to the top surface of the substrate and perpendicular to the first direction, and
in a plan view, a first end portion of each of the plurality of first gate electrodes protrudes outwards in the first direction with respect to a second end portion of each of the plurality of second gate electrodes,
wherein the plurality of first gate electrodes include,
first work function control conductive layers on inner walls of the plurality of first trenches, and
first buried conductive layers on the first work function control conductive layers, and
the plurality of second gate electrodes include,
second work function control conductive layers on inner walls of the plurality of second trenches;
and
second buried conductive layers on the second work function control conductive layers.

9 more elements

An integrated circuit device comprising:

device isolation layers in a substrate and defining a plurality of active areas;
a plurality of first gate electrodes in a plurality of first trenches in the substrate and extending in a first direction parallel to a top surface of the substrate;
and
a plurality of second gate electrodes in a plurality of second trenches in the substrate and extending in the first direction,
wherein the plurality of first trenches alternate with the plurality of second trenches in a second direction, the second direction parallel to the top surface of the substrate and perpendicular to the first direction, and
in a plan view, a first end portion of each of the plurality of first gate electrodes protrudes outwards in the first direction with respect to a second end portion of each of the plurality of second gate electrodes,
wherein the plurality of first trenches comprise first portions vertically overlapping the plurality of active areas and second portions vertically overlapping the device isolation layers,
the plurality of second trenches comprise third portions vertically overlapping the plurality of active areas and fourth portions vertically overlapping the device isolation layers,
bottom surfaces of the first portion are at the same level as bottom surfaces of the third portions, and
bottom surfaces of the second portions are at the same level as bottom surfaces of the fourth portions.

7 more elements

Dependencies are inferred from the claim text.

Facts

Application: 17/744,026Filed 13 May 2022 · division
Priority: KR 10-2019-01233504 Oct 2019
Published: US 2022/0271043 A125 Aug 2022
Granted: 16 Apr 2024
Term ends: Not estimatedThe source records don’t support an estimate.

Classification11 codes

H10B 12/053
Making the transistor: the transistor being at least partially in a trench in the substrate
H10B 12/34
DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells: the transistor being at least partially in a trench in the substrate
H10B 12/488
Data lines or contacts therefor: word lines
H10P 50/642
Of semiconductor materials: chemical etching

Family

Application16/902,506Parent of this division · filed 16 Jun 2020
US 2022/0271043 A1Pre-grant publication · published 25 Aug 2022
US 11,355,498 B2Parent of this division
US 2021/0104529 A1Published application
US 11,963,344 B2This patent

From the US filing history. Foreign family members aren’t listed.