Load reduced memory module
AssigneeRambus Inc.
InventorsFrederick A. Ware, Suresh Rajan
Life of this patent
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Abstract
The embodiments described herein describe technologies for memory systems. One implementation of a memory system includes a motherboard substrate with multiple module sockets, at least one of which is populated with a memory module. A first set of data lines is disposed on the motherboard substrate and coupled to the module sockets. The first set of data lines includes a first subset of point-to-point data lines coupled between a memory controller and a first socket and a second subset of point-to-point data lines coupled between the memory controller and a second socket. A second set of data lines is disposed on the motherboard substrate and coupled between the first socket and the second socket. The first and second sets of data lines can make up a memory channel.
Claims20
A command and address (CA) buffer device to be disposed on a first memory module, the CA buffer device comprising:
- a primary interface comprising a first terminal to receive a first chip select (CS) signal from a memory controller and a second terminal to receive a second CS signal from a second memory module;
- and
- a secondary interface to select a first set of one or more of a plurality of device sites of the first memory module when the first CS signal is received on the first terminal or a second set of one or more of the plurality of device sites when the second CS signal is received on the second terminal, wherein each device site of the plurality of device sites is a location at which at least one memory device is disposed.
A method of operating a command and address (CA) buffer device of a first memory module comprising a plurality of device sites, each device site, of the plurality of device sites, being a location on a circuit board at which at least one respective memory device is disposed, the method comprising:
- receiving, at a first terminal of a primary interface of the CA buffer device, a first chip select (CS) signal from a memory controller;
- receiving, at a second terminal of the primary interface, a second CS signal from a second memory module;
- when the first CS signal is received on the first terminal, selecting on a secondary interface of the CA buffer device a first set of one or more of a plurality of device sites;
- and
- when the second CS signal is received on the second terminal, selecting a second set of one or more of the plurality of device sites.
A command and address (CA) buffer device to be disposed on a first memory module, the CA buffer device comprising:
- a primary interface comprising a first terminal to receive a first chip select (CS) signal from a memory controller and a second terminal to receive a second CS signal from a second memory module;
- and
- means for selecting a first set of one or more of a plurality of device sites of the first memory module when the first CS signal is received, wherein each device site of the plurality of device sites is a location at which at least one memory device is disposed;
- and
- means for selecting a second set of one or more of the plurality of device sites when the second CS signal is received.
Dependencies are inferred from the claim text.