Spread spectrum high-speed serial link

A method for clocking a high-speed data communication interface having a number (N) of lanes, the method comprising:

• providing, by a triangle wave generator of a clock circuit of the high-speed data communication interface, a number (P) of phase outputs, wherein P is greater than or equal to N;
• receiving, by each one of a number (N) of clock generators of the clock circuit, an associated one of the phase outputs;
• generating, by each clock generator, a clock signal having a frequency based upon the phase output;
• receiving, by each one of a number (N) of lane first-in/first-out buffers (FIFOs), data and an associated one of the clock signals;
• and
• providing, by each FIFO, the data at a clock frequency associated with the associated clock signal;
• wherein N is equal to sixteen, and the order provides a 0th clock signal to the FIFO associated with a 1st lane, a 1st clock signal to the FIFO associated with a 5th lane, a 2nd clock signal to the FIFO associated with a 9th lane, a 3rd clock signal to the FIFO associated with a 13th lane, a 4th clock signal to the FIFO associated with a 0th lane, a 5th clock signal to the FIFO associated with a 4th lane, a 6th clock signal to the FIFO associated with an 8th lane, a 7th clock signal to the FIFO associated with a 12th lane, an 8th clock signal to the FIFO associated with a 14th lane, a 9th clock signal to the FIFO associated with a 10th lane, a 10th clock signal to the FIFO associated with a 6th lane, an 11th clock signal to the FIFO associated with a 2nd lane, a 12th clock signal to the FIFO associated with a 15th lane, a 13th clock signal to the FIFO associated with an 11th lane, a 14th clock signal to the FIFO associated with a 7th lane, and a 15th clock signal to the FIFO associated with a 3rd lane.

An information handling system, comprising:

• a transmitter;
• and
• a receiver coupled to the transmitter by a high-speed data communication interface having a number (N) of lanes;
• wherein the transmitter includes a clock circuit for clocking the high-speed data communication interface, the clock circuit including:
• a triangle wave generator that provides a number (P) of phase outputs, wherein P is greater than or equal to N;
• a number (N) of clock generators, wherein each clock generator receives an associated one of the phase outputs and generates a clock signal having a frequency based upon the phase output;
• and
• a number (N) of lane first-in/first-out buffers (FIFOs), wherein each receives data and an associated one of the clock signals, and provides the data at a clock frequency associated with the associated clock signal;
• and
• wherein the receiver asynchronously decodes the data from the high-speed data communication interface;
• and
• wherein N is equal to eight (8), and the order provides a 0th clock signal to the FIFO associated with a 1st lane, a 1st clock signal to the FIFO associated with a 5th lane, a 2nd clock signal to the FIFO associated with a 0th lane, a 3rd clock signal to the FIFO associated with a 4th lane, a 4th clock signal to the FIFO associated with a 6th lane, a 5th clock signal to the FIFO associated with a 2nd lane, a 6th clock signal to the FIFO associated with a 7th lane, and a 7th clock signal to the FIFO associated with a 3rd lane.