Decision feedback equalizer for low-voltage high-speed serial links

A method of operating a comparator, the comparator including a first inverter, a second inverter cross-coupled with the first inverter, a first drive transistor coupled to the first inverter, and a second drive transistor coupled to the second inverter, wherein a gate of the second drive transistor is coupled to a first node, and a gate of the first drive transistor is coupled to a second node, further wherein the comparator further includes a first offset transistor coupled to the second node, and a second offset transistor coupled to the first node, the method comprising:

• if a previous bit value is one,
• comparing an input voltage with a first compare voltage using a first input circuit, the first compare voltage including a first offset-cancellation component, and
• generating a first voltage on the first node and a second voltage on the second node based on the comparison of the input voltage with the first compare voltage;
• if the previous bit value is zero,
• comparing the input voltage with a second compare voltage using a second input circuit, the second compare signal including a second offset-cancellation component, wherein the first offset-cancellation component and the second offset-cancellation component contribute to cancellation of an offset voltage of the comparator, and
• generating the first voltage on the first node and the second voltage on the second node based on the comparison of the input voltage with the second compare voltage;
• using a first digital-to-analog converter (DAC) to generate a first offset-cancellation voltage;
• inputting the first offset-cancellation voltage to a gate of the first offset transistor;
• using a second digital-to-analog converter (DAC) to generate a second offset-cancellation voltage;
• and
• inputting the second offset-cancelation voltage to a gate of the second offset transistor, wherein the first offset-cancellation voltage and the second offset-cancellation voltage contribute to the cancellation of the offset voltage of the comparator.

A system, comprising:

• a comparator comprising:
• an input stage, comprising:
• a first input circuit coupled to a first node and a second node, the first input circuit configured to receive an input of the comparator and a first compare voltage including a first offset-cancellation component;
• a first switching transistor configured to enable the first input circuit if a previous bit value is one;
• a second input circuit coupled to the first node and the second node, the second input circuit configured to receive an input of the comparator and a second compare voltage including a second offset-cancellation component, component, wherein the first offset-cancellation component and the second offset-cancellation component contribute to cancellation of an offset voltage of the comparator;
• and
• a second switching transistor configured to enable the second input circuit if the previous bit value is zero;
• a regeneration stage, comprising:
• a first inverter;
• a second inverter cross coupled with the first inverter, wherein a first output of the comparator is coupled to an output of the second inverter and a second output of the comparator is coupled to an output of the first inverter;
• a first drive transistor coupled to the first inverter, wherein a gate of the first drive transistor is coupled to the second node;
• and
• a second drive transistor coupled to the second inverter, wherein a gate of the second drive transistor is coupled to the first node, wherein the input stage and the regeneration stage are arranged in parallel between a supply rail and a ground;
• and
• an offset cancellation circuit, comprising:
• a first offset transistor coupled to the second node, wherein a gate of the first offset transistor is configured to receive a first offset-cancellation voltage;
• and
• a second offset transistor coupled to the first node, wherein a gate of the second offset transistor is configured to receive a second offset-cancellation voltage, and the offset cancellation circuit contributes to the cancellation of the offset voltage of the comparator;
• and
• a latch having a first input and a second input, wherein the first input of the latch is coupled to the first output of the comparator, and the second input of the latch is coupled to the second output of the comparator.