Fast equalization for jitter mitigation

A system for receiving a data signal transmitted via serial links, comprising:

• a timing recovery loop comprising:
• an analog to digital converter coupled to the output of a media receiver;
• an equalizer coupled to an output of the digital converter;
• a slicer coupled to an output of the equalizer;
• a phase detector coupled to the output of the slicer;
• a loop filter coupled to the output of the phase detector;
• a phase interpolator coupled to the output of the loop filter,
• wherein the phase interpolator provides a clock signal input to the analog to digital converter to trigger sampling of the output of the media receiver;
• a fast equalizer, coupled to the timing recovery loop, comprising:
• a filter coupled to an output of the equalizer and configured to receive filter coefficients from a lookup table;
• a coefficient improver coupled to an output of the equalizer and configured to receive an error signal from the filter,
• wherein the coefficient improver is further configured to update filter coefficients in the lookup table;
• a low pass filter coupled to an output of the phase detector and configured to provide an index address to the lookup table to select the filter coefficients for use by the filter;
• and
• a slicer coupled to an output of the filter and providing a data output signal corresponding to the data signal.

A method of fast equalization for mitigating jitter in clock signals recovered from received serial communication, the method comprising:

• filtering equalized data to produce filtered data,
• wherein the filtering utilizes filtering coefficients accessed from a lookup table;
• accessing the filtering coefficients from the lookup table utilizing an index address provided by a low pass filter;
• and
• slicing the filtered data to produce a data signal corresponding to the received serial communication.