Iterative decoding technique for correcting DRAM device failures
AssigneeMicron Technology, Inc.
InventorsJoseph M. McCrate, Nevil Gajera, Mohammed Ebrahim Hargan
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Abstract
Provided is a memory system comprising a plurality of memory components; and a controller in communication with the plurality of memory components and configured to perform error correction code (ECC) decoding on a received word read from the plurality of memory components. The ECC decoding is configured to (i) detect one or more random errors in a portion of the received word, the portion corresponding to one of the components within the plurality, and (ii) correct the detected random errors; and when the correcting of the detected random errors fails, iteratively marking symbols in the remaining portions of the received word as erasures.
Claims21
A memory system comprising:
- a plurality of memory components;
- and
- a controller in communication with the plurality of memory components and configured to:
- perform error correction code (ECC) decoding on a received word read from the plurality of memory components
- comprising:
- (i) performing a single decoding attempt to detect one or more random errors in a portion of the received word, the portion corresponding to one memory component within the plurality of memory components, and correct the detected random errors;
- and
- (ii) when the correcting of the detected random errors fails, iteratively performing decoding attempts with each attempt marking symbols in the remaining portions of the received word that correspond respectively to remaining memory components of the plurality of memory components, as erasures, and using counter logic to obtain erasure location information corresponding to the erasures.
A method comprising:
- performing, in a controller of a memory system including a plurality of memory components, error correction code (ECC) decoding on a received word read from the plurality of memory components
- by (i) performing a single decoding attempt to detect one or more random errors in a portion of the received word, the portion corresponding to one memory component within the plurality of memory components, and correct the detected random errors;
- and
- (ii) when the correcting of the detected random errors fails, iteratively performing decoding attempts with each attempt marking symbols in the remaining portions of the received word that correspond respectively to remaining memory components of the plurality of memory components, as erasures, and using counter logic to obtain erasure location information corresponding to the erasures.
A non-transitory computer readable medium having stored thereon computer executable instructions that, if executed by a computing device, cause the computing device to perform a method for use by a memory controller of a memory system including a plurality of memory components, the method comprising:
- performing, in a controller of a memory system including a plurality of memory components, error correction code (ECC) decoding on a received word read from the plurality of memory components
- by (i) performing a single decoding attempt to detect one or more random errors in a portion of the received word, the portion corresponding to one memory component within the plurality of memory components, and correct the detected random errors;
- and
- (ii) when the correcting of the detected random errors fails, iteratively performing decoding attempts with each attempt marking symbols in the remaining portions of the received word that correspond respectively to remaining memory components of the plurality of memory components, as erasures, and using counter logic to obtain erasure location information corresponding to the erasures.
Dependencies are inferred from the claim text.