Calibration and alignment

Calibration circuitry comprising:

• delay circuitry configured to apply a delay to a synchronization clock signal and output a delayed synchronization clock signal;
• a phase detector configured to measure a phase difference between the delayed synchronization clock signal and a target clock signal and output a measurement signal indicating the phase difference;
• a comparator configured to compare the measurement signal to a reference signal and output a comparison signal;
• and
• control circuitry configured to, based on the comparison signal, adjust the delay applied to the synchronization clock signal by the delay circuitry to bring the delayed synchronization clock signal and the target clock signal into or towards a target phase relationship.

Calibration and alignment circuitry comprising:

• calibration circuitry comprising:
• delay circuitry configured to apply a delay to a synchronization clock signal and output a delayed synchronization clock signal;
• a phase detector configured to measure a phase difference between the delayed synchronization clock signal and a target clock signal and output a measurement signal indicating the phase difference;
• a comparator configured to compare the measurement signal to a reference signal and output a comparison signal;
• and
• control circuitry configured to, based on the comparison signal, adjust the delay applied to the synchronization clock signal by the delay circuitry to bring the delayed synchronization clock signal and the target clock signal into or towards a target phase relationship, and
• alignment circuitry comprising:
• a first clocked latch configured to receive a synchronization signal having an enable edge and a target clock signal and to output an enable signal having an enable edge corresponding to the enable edge of the synchronization signal and synchronized with the target clock signal;
• a second clocked latch configured to receive the enable signal and a delayed target clock signal, being a version of the target clock signal having been delayed by a delay circuit of the clock-controlled circuitry, and to output a re-timed enable signal having an enable edge corresponding to the enable edge of the enable signal and synchronized with the delayed target clock signal;
• and
• gating circuitry configured to receive the delayed target clock signal and the re-timed enable signal and to start output of the delayed target clock signal at a timing defined by the enable edge of the re-timed enable signal for controlling the clock-controlled circuitry,
• wherein the alignment circuitry is configured to receive the delayed synchronization clock signal output from the calibration circuitry as the synchronization signal.