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AssigneeSocionext Inc.
InventorsKenichi Okada, Hanli Liu, Zheng Sun
Estimating the term…
With respect to a phase locked loop (PLL) circuit that receives a first reference clock and generates an output clock, the PLL circuit includes a delay circuit that delays the first reference clock to generate a second reference clock, a feedback circuit that generates a control signal based on a phase difference between the second reference clock and a feedback clock, an oscillator that oscillates at a frequency determined based on the control signal to generate the output clock, and a divider that divides the output clock in the on state. The PLL circuit switches between a first mode and a second mode, the feedback clock in the first mode is a signal obtained by retiming an output of the divider with the output clock, and the feedback clock in the second mode is a signal obtained by retiming the first reference clock with the output clock.
A phase locked loop circuit that receives a first reference clock and generates an output clock, the phase locked loop circuit comprising:
A digitally-controlled oscillator comprising:
A digital-to-time convertor that receives an input signal and applies a delay corresponding to a control code to generate an output signal, the digital-to-time convertor comprising:
Dependencies are inferred from the claim text.