Adaptive DCO VF curve slope control

A system comprising:

• a plurality of components in an integrated circuit, the integrated circuit including a clock tree;
• a frequency locked loop circuit that generates a system clock that drives the clock tree;
• and
• an oscillator circuit within the frequency locked loop circuit comprising:
• a first delay line having a signal input, a supply input for receiving a first voltage, and an output that transmits a first delayed signal at a first delay proportional to the first voltage;
• a second delay line having a signal input, a supply input for receiving a second voltage, and an output that transmits a second delayed signal at a second delay proportional to the second voltage;
• an edge detector having two inputs connected to the respective outputs of the first and second delay lines and generating an output clock based on a relationship between the first delayed signal and the second delayed signal, the output clock applied to the signal inputs of the first and second delay lines, the output clock exhibiting a voltage dependent frequency performance curve having a slope dependent at least on the second delay and a delay characteristic of the edge detector;
• wherein at least one of the first delay line, the second delay line, and the edge detector are operable to adjust the slope by altering the delay characteristic of the edge detector relative to at least one of the first and second delays and compensate for a change in frequency of the oscillator circuit due to the slope adjustment.

A method of clock frequency adjustment in an oscillator circuit comprising:

• connecting a first delay line to a regulated supply voltage and causing the first delay line to transmit a first delayed signal at a first delay proportional to the regulated supply voltage;
• connecting a second delay line to a droopy supply voltage and causing the second delay line to transmit a second delayed signal at a second delay proportional to the droopy supply voltage;
• connecting the first and second delay lines to first and second inputs of an edge detector that generates an output clock, the output clock exhibiting a voltage dependent frequency performance curve having a slope dependent at least on the second delay and a delay characteristic of the edge detector;
• feeding the output clock as an input to the first and second delay lines;
• and
• adjusting the slope by altering the delay characteristic of the edge detector relative to at the one of the first and second delays and compensating for a change in frequency of the oscillator circuit due to the slope adjustment.