Sub-sampling phase locked loop with compensated loop bandwidth and integrated circuit including the same

An integrated circuit comprising:

• a sub-sampling phase locked loop (PLL) configured to generate an output clock signal based on a reference clock signal;
• and
• an internal circuit configured to operate based on the output clock signal,
• wherein the sub-sampling phase locked loop includes
• a slope generating and sampling circuit configured to generate a sampling voltage based on the reference clock signal and the output clock signal,
• a first transconductance circuit configured to generate a first output control voltage based on the sampling voltage, a reference voltage, and a control current,
• a second transconductance circuit configured to generate a second output control voltage based on the sampling voltage, the reference voltage, and the control current,
• a constant transconductance bias circuit including a switched capacitor resistor (SCR), the constant transconductance bias circuit configured to generate the control current,
• a loop filter connected to an output terminal of the first transconductance circuit and an output terminal of the second transconductance circuit, and
• a voltage controlled oscillator (VCO) configured to generate the output clock signal based on the first output control voltage and the second output control voltage,
• wherein the constant transconductance bias circuit further includes,
• a first circuit connected between a power supply voltage and a ground voltage, and
• a second circuit connected to the power supply voltage and the first circuit, and configured to output the control current, and
• wherein the switched capacitor resistor is connected between the first circuit and the ground voltage and the switched capacitor resistor is configured to operate based on a first phase signal and a second phase signal.

A sub-sampling phase locked loop (PLL) comprising:

• a slope generating and sampling circuit including a first resistor and a first capacitor, the slope generating and sampling circuit configured to generate a sampling voltage based on a reference clock signal and an output clock signal, a slope of the sampling voltage being inversely proportional to a resistance of the first resistor and a capacitance of the first capacitor;
• a constant transconductance bias circuit including a switched capacitor resistor (SCR) including a second capacitor, the constant transconductance bias circuit configured to generate a control current, a current level of the control current being proportional to a capacitance of the second capacitor;
• a first transconductance circuit configured to generate a first output control voltage based on the sampling voltage, a reference voltage, and a control current, a voltage level of the first output control voltage being proportional to a resistance of a second resistor and the capacitance of the second capacitor;
• a second transconductance circuit configured to generate a second output control voltage based on the sampling voltage, the reference voltage, and the control current;
• a loop filter including the second resistor, the loop filter connected to an output terminal of the first transconductance circuit and an output terminal of the second transconductance circuit;
• and
• a voltage controlled oscillator (VCO) configured to generate the output clock signal based on the first output control voltage and the second output control voltage, wherein
• a proportional path of the sub-sampling phase locked loop is formed by the first transconductance circuit,
• an integral path of the sub-sampling phase locked loop is formed by the second transconductance circuit,
• a loop bandwidth of the sub-sampling phase locked loop is independent of the resistance of the first resistor, the capacitance of the first capacitor, the resistance of the second resistor, and the capacitance of the second capacitor, and
• the loop bandwidth of the sub-sampling phase locked loop is proportional to a gain of the proportional path.