Successive-approximation register analog-to-digital converter circuit and operating method thereof

A successive-approximation register (SAR) analog-to-digital converter (ADC) circuit, comprising:

• a comparator circuit, configured to compare an analog signal with a plurality of reference levels in a plurality of comparison cycles, respectively;
• and
• a plurality of latch circuits, coupled to the comparator circuit and connected in series, the latch circuits being triggered sequentially in response to a plurality of trigger signals, respectively, to store a comparator output of the comparator circuit generated in the comparison cycles, respectively, and accordingly generate a digital signal, wherein a first latch circuit and a second latch circuit of the latch circuits are triggered in response to a first trigger signal and a second trigger signal of the trigger signals, respectively;
• the first latch circuit is configured to generate the second trigger signal according to the comparator output stored in the first latch circuit;
• wherein the first latch circuit comprises a circuit terminal and a set of input terminals different from the circuit terminal, the circuit terminal is arranged to receive the first trigger signal, and the set of input terminals is coupled to the comparator output of the comparator circuit;
• the first latch circuit is enabled by the first trigger signal to receive the comparator output generated in a corresponding comparison cycle before the comparator output generated in the corresponding comparison cycle reaches a valid logic state.

A successive-approximation register (SAR) analog-to-digital converter (ADC) circuit, comprising:

• a comparator circuit, configured to compare an analog signal with a plurality of reference levels in a plurality of comparison cycles, respectively;
• and
• a plurality of latch circuits, coupled to the comparator circuit and connected in series, the latch circuits being triggered sequentially in response to a plurality of trigger signals, respectively, to store a comparator output of the comparator circuit generated in the comparison cycles, respectively, and accordingly generate a digital signal, wherein a first latch circuit and a second latch circuit of the latch circuits are triggered in response to a first trigger signal and a second trigger signal of the trigger signals, respectively;
• the first latch circuit is configured to generate the second trigger signal according to the comparator output stored in the first latch circuit;
• wherein the second latch circuit comprises a circuit terminal and a set of input terminals different from the circuit terminal, the circuit terminal is arranged to receive the second trigger signal, and the set of input terminals is coupled to the comparator output of the comparator circuit;
• the second latch circuit is enabled by the second trigger signal to receive the comparator output generated in a corresponding comparison cycle before the comparator output generated in the corresponding comparison cycle reaches a valid logic state.