Clock anomaly detection
AssigneeNVIDIA Corporation
InventorKedar Rajpathak
Life of this patent
Estimating the term…
Abstract
Methods and apparatus are described for detecting anomalies in a clock signal. Example methods include sensing a clock signal that exhibits alternating phases during normal operation; responsive to sensing the start of a first phase, generating a pulse; and if the pulse terminates before sensing the end of the first phase, asserting a clock stopped detection signal. Example clock anomaly detection apparatus includes a clock signal input for coupling to a clock signal that, during normal operation, oscillates between first and second clock states. An anomaly detection output is asserted if the clock signal remains in the first clock state longer than a first phase expected duration or remains in the second clock state longer than a second phase expected duration.
Claims30
A method, comprising:
- a) sensing a clock signal that exhibits cycles during normal operation, each cycle including two opposite state phase instances having respective first and second expected durations, and each phase instance having a beginning and an end;
- b) responsive to sensing the beginning of a first phase instance, starting a first timer having a first timer duration at least as long as the first expected duration, wherein starting the first timer comprises generating a first pulse having a duration corresponding to the first timer duration;
- c) comparing the first pulse with at least one version of the clock signal to determine if the first timer expires before the end of the first phase instance;
- and
- d) if the first timer expires before the end of the first phase instance, asserting a first clock stop detection signal, else if the first timer does not expire before sensing the end of the first phase instance, resuming at step b.
Clock anomaly detection circuitry, comprising:
- a clock signal input for coupling to a clock signal that, during normal operation, oscillates between first and second clock states, wherein the first clock state corresponds to a first phase having a first phase expected duration and the second clock state corresponds to a second phase having a second phase expected duration;
- an anomaly detection output;
- and
- clock stopped detection logic coupled to the clock signal input and operable to assert the anomaly detection output if the clock signal remains in the first clock state longer than the first phase expected duration or remains in the second clock state longer than the second phase expected duration;
- wherein
- a first edge of the clock signal signifies a start of a new clock phase having a new phase expected duration equal to one of the first or the second phase expected durations;
- and
- the clock stopped detection logic comprises:
- at least one edge triggered pulse generator that, when triggered responsive to the first edge of the clock signal, generates a pulse at a pulse output, the pulse having a pulse duration at least as long the new phase expected duration but not longer than an expected cycle time of the clock signal;
- and
- one or more Boolean logic circuits configured to compare the pulse output with at least one version of the clock signal and, based on the comparison, to indicate if the pulse ends before the clock signal exhibits a second edge in a direction opposite to that of the first edge.
Dependencies are inferred from the claim text.